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100GbE IP Core RX Client Interface Examples
Example on RX Client Interface Without Preamble Pass-Through
Figure 3-26: Typical Traffic on the RX Client Interface for 100GbE IP Core Without Adapters and with
Preamble Pass-Through Turned Off
/e100_tb/dut/dout_d
070707070707070...363738393a3b3c3...5e5f606162636465... 020202020202010...8788898a8b8c8d8...afb0b1b2b3b4b5b6... fb55555070707070707070...
/e100_tb/dut/dout_c
000007ffff
ffffffff80
ffffffffff
000000003f
0000000000 0000000000
800
10
08
00 00
/e100_tb/dut/dout_first_data
0000800000 0000000400 00000000000000000000
/e100_tb/dut/dout_last_data
00
00
/e100_tb/dut/dout_runt_last_data
1f 1c 00 1f 1e 00 0f
/e100_tb/dut/dout_payload
/e100_tb/dut/dout_fcs_error
/e100_tb/dut/dout_fcs_valid
00
/e100_tb/dut/dout_dst_addr_match
/e100_tb/dut/dout_valid
/e100_tb/dut/clk_rxmac
1
2
3 4
5
6 7
8
In the figure, dout_last_data is asserted in the second cycle, indicating the end of a packet. The dout_d
signal returns to 0 (5’h1c = 5’b11100). The dout_c and dout_d busses are set to 1b’1 and 8’h07,
respectively, to indicate idling. In the fourth cycle, dout_first_data is asserted and a short packet begins.
This packet terminates successfully in the final cycle. Note that the first packet has a CRC error
(dout_fcs_error = 1 and fcs_valid = 1).
The dout_first_data signal marks the first word of data. The first byte of data is always the most signifi‐
cant byte of the word. There are 5 legal starting positions for the 100GbE IP core and 2 legal starting
positions for the 40GbE IP core. The dout_last_data signal marks the last data byte before the FCS
(CRC). It can occur at any byte position.
The dout_runt_last_data signal indicates that the packet ending in this word is less than the minimum
legal length of 64 bytes from first data to the last FCS byte inclusive. Runt frames of eight or fewer bytes
cannot be legally represented in CGMII and trigger a decoding error rather than this flag.
The dout_fcs_error and dout_fcs_valid signals indicate the result of the CRC checking logic.
dout_fcs_valid = 1 and dout_fcs_error = 1 indicate a corrupted frame. Note that the CRC checking
network works correctly on runt frames of 40–63 bytes. Runt frames of less than 40 bytes may be
incorrectly determined to have a proper CRC.
3-30
100GbE IP Core RX Client Interface Examples
UG-01088
2014.12.15
Altera Corporation
Functional Description
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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