Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuale Utente Pagina 52
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Related Information
MAC Address Registers on page 3-107
Includes information about the MADDR_CTRL, SRC_AD_LO, and SRC_AD_HI registers.
Length/Type Field Processing
This two-byte header represents either the length of the payload or the type of MAC frame. When the
value of this field is equal to or greater than 1536 (0x600) it indicates a type field. Otherwise, this field
provides the length of the payload data that ranges from 0–1500 bytes. The TX MAC does not modify this
field before forwarding it to the network.
Frame Padding
When the length of client frame is less than 64 bytes (meaning the payload is less than 46 bytes), the TX
MAC module inserts pad bytes (0x00) after the payload to create a frame length equal to the minimum
size of 64 bytes.
Frame Check Sequence (CRC-32) Insertion
The TX MAC computes and inserts a CRC32 checksum in the transmitted MAC frame. The frame check
sequence (FCS) field contains a 32-bit CRC value. The MAC computes the CRC32 over the frame bytes
that include the source address, destination address, length, data, and pad. The CRC checksum computa‐
tion excludes the preamble, SFD, and FCS. The encoding is defined by the following generating
polynomial:
FCS(X) = X32 +X26 +X23 +X22 +X16 +X12 +X11 +X10 +X8 +X7 +X5 +X4 +X2 +X1 +1
CRC bits are transmitted with MSB (X32) first.
Independent user configuration register bits control FCS CRC insertion at runtime. Bit [0] of the
CRC_CONFIG register enables and disables CRC insertion. By default, the CRC insertion feature is enabled.
Related Information
• Order of Transmission on page 3-16
Illustrations of the byte order and octet transmission order on the Avalon-ST client interface.
• CRC Configuration Register on page 3-105
Information about the CRC_CONFIG register.
Inter‑Packet Gap Generation and Insertion
The TX MAC maintains the minimum inter-packet gap (IPG) between transmitted frames required by
the IEEE 802.3 Ethernet standard. The standard requires an average minimum IPG of 96 bit times (or 12
byte times). The deficit idle counter maintains the average IPG of 12 bytes.
The MAC adjusts the IPG to compensate for Alignment Marker insertion by the PHY. You can program
this adjustment using the IPG_DEL_PERIOD and IPG_DEL_ENABLE registers at offsets 0x126 and 0x127,
respectively. By default, the adjustment removes one Idle byte for every 16384 bytes. This removal rate
corresponds to the bandwidth used by the Alignment Marker that the PHY inserts in the outgoing
Ethernet communication. You can modify the value in the IPG_DEL_PERIOD register to specify more or
less frequent removal of Idle bytes from the sequence.
UG-01088
2014.12.15
Length/Type Field Processing
3-5
Functional Description
Altera Corporation
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- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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