Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuale Utente Pagina 160
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Address Name- Description Access
0x28A CNTR_RX_
1024to1518B_LO
Number of received frames between 1024–1518 bytes (lower
32 bits)
RO
0x28B CNTR_RX_
1024to1518B_HI
Number of received frames between 1024–1518 bytes (upper
32 bits)
RO
0x28C CNTR_RX_
1519toMAXB_LO
Number of received frames between 1519 and the maximum
size defined in 0x103 (lower 32 bits)
RO
0x18D CNTR_RX_
1519toMAXB_HI
Number of received frames between 1519 and the maximum
size defined in 0x103 (upper 32 bits)
RO
0x28E CNTR_RX_
OVERSIZE_LO
Number of oversized frames received (lower 32 bits) RO
0x28F CNTR_RX_
OVERSIZE_HI
Number of oversized frames received (upper 32 bits) RO
0x290 CNTR_RX_MCAST_
DATA_ERR_LO
Number of errored multicast frames received, excluding
control frames (lower 32 bits)
RO
0x291 CNTR_RX_MCAST_
DATA_ERR_HI
Number of errored multicast frames received, excluding
control frames (upper 32 bits)
RO
0x292 CNTR_RX_MCAST_
DATA_OK_LO
Number of valid multicast frames received, excluding
control frames (lower 32 bits)
RO
0x293 CNTR_RX_MCAST_
DATA_OK_HI
Number of valid multicast frames received, excluding
control frames (upper 32 bits)
RO
0x294 CNTR_RX_BCAST_
DATA_ERR_LO
Number of errored broadcast frames received, excluding
control frames (lower 32 bits)
RO
0x295 CNTR_RX_BCAST_
DATA_ERR_HI
Number of errored broadcast frames received, excluding
control frames (upper 32 bits)
RO
0x296 CNTR_RX_BCAST_
DATA_OK_LO
Number of valid broadcast frames received, excluding
control frames (lower 32 bits)
RO
0x297 CNTR_RX_BCAST_
DATA_OK_HI
Number of valid broadcast frames received, excluding
control frames (upper 32 bits)
RO
0x298 CNTR_RX_UCAST_
DATA_ERR_LO
Number of errored unicast frames received, excluding
control frames (lower 32 bits)
RO
0x299 CNTR_RX_UCAST_
DATA_ERR_HI
Number of errored unicast frames received, excluding
control frames (upper 32 bits)
RO
UG-01088
2014.12.15
Statistics Registers
3-113
Functional Description
Altera Corporation
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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