Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuale Utente Pagina 195
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Date ACDS
Version
Changes
• If you are transitioning from an earlier version of the IP core, you must
complete the following steps:
• Generate the 12.1 release from the MegaWizard Plug-In Manager
into a new project directory; this will generate a .qip file to include in
the Quartus II software project, along with the required Verilog HDL
files. For more information, refer to “Getting Started” on page 2–1.
• Quartus II software assignments from previous releases that
reference the internal IP hierarchy (such as logic lock regions) must
be updated for changes in the internal hierarchy. Hierarchy changes
include the following:
• The top-level Verilog in the synthesis file set has one level below it
named <name of your IP instance>_inst. All further instances
begin under the <name of your IP instance>_inst directory.
• The pcs_tx, pcs_rx, and phy_csr instances now reside under
phy/phy_pcs
• The pcs_tx, pcs_rx, and phy_csr instances now reside under
phy/phy_pcs
• Nodes for the Stratix V device PMA now reside under phy/pma/
pma_bridge
• Generate example designs from the 12.1 release of the MegaWizard
Plug-In Manager for a complete set of new Quartus II software
assignments
• The reconfiguration controller must be instantiated and connected to
the IP core. For more information, refer to “External Reconfiguration
Controller” on page 3–26 and “12.1 Example Design” on page A–1
• Note the GXB_0PPM_CORECLK and GXB_0PPM_CORE_CLOCK Quartus II
software settings are no longer required.
• Feature additions:
• 40GbE Lower Rate 24.24 Gbps MAC and PHY
• 100GbE CAUI–4 PHY
• RX Automatic Pad Removal Control
• Pause Control Frames Filtering Control
• Updated or added signals:
• Top-level output and input high-speed serial lines from the
transceivers
• External reconfiguration controller
• TX MAC to PHY connections
• RX MAC to PHY connections
• Added registers:
• PAD_CONFIG at offset 0x124
• Low Latency PHY IP Core registers for CAUI–4 at offsets 0x800–
0x9FF, 0xA00–0xBFF, 0xC00–0xDFF, and 0xE00–0xFFF.
D-6
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision
History
UG-01088
2014.12.15
Altera Corporation
Additional Information
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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