Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuale Utente Pagina 164
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Address Name Bits Description HW Reset Value Access
0x403 CMD_STATUS
[6] PMD global alarm. 1b’0 R
[5] Programmable alarm 3. Defaults to
module ready.
1b’0 R
[4] Programmable alarm 2. Defaults to
high power mode on.
1b’0 R
[3] Programmable alarm 1. Defaults to RX
CDR lock.
1b’0 R
[2] RX side signal detected. 1’b0 R
[1] When asserted, the PMD module is
physically plugged in. When
deasserted, it is offline.
1b’1 R
[0] When 1, the PMD is resetting. When 0,
the PMD is available.
1’b1 R
Related Information
• 40-100GbE IP Core Example Design on page 5-1
Altera provides an example design with the 40-100GbE IP core. This example design is ready for
compilation and can be configured on a target device. The listed registers are part of the example
design.
• CFP Multi-Source Agreement website
For more information about PMD devices, refer to the Next Gen PMD CFP MSA Baseline Specifica‐
tions available on the CFP Multi-Source Agreement website.
MDIO Registers
The management data input/output (MDIO) interface is a serial bus interface for the Ethernet. In the
40-100GbE IP core example design, client logic drives the MDIO module when an MDIO serial interface
controls the external PMD or CFP device. This serial interface includes two wires, an MDC clock driven
by the MAC and a bidirectional data line which can be driven by up to 31 PHY slave devices. The
minimum clock frequency is 2.5 MHz. Refer to the specification of your PMD or CFP device for
additional information.
Table 3-51: MDIO Registers
Describes the MDIO registers in the 40-100GbE IP core example design. These registers are typically used to
communicate with an external optical module such as a PMD 100G optical module.
Address Name Bits Description HW Reset Value Access
0x410 MDIO_WDATA [15:0] Data to be written. 0x0000 RW
UG-01088
2014.12.15
MDIO Registers
3-117
Functional Description
Altera Corporation
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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