Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuale Utente Pagina 28
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Table 2-2: 40-100GbE Parameters: 40GBASE-KR4 Tab
Describes the parameters for customizing a 40GBASE-KR4 40-100GbE IP core, on the 40GBASE-KR4 tab of the
40-100GbE parameter editor. The parameters on this tab are available only if the following conditions hold:
• Your IP core targets a Stratix V device. You set the target device family for your Quartus II project or in the
Quartus II software before you acess the IP Catalog.
• You select the value of 40 GbE for the MAC configuration parameter on the Main tab.
• You select a Core option value that includes a PHY component (PHY or MAC & PHY) on the Main tab.
• You select the value of 40 Gbps (4x10) for the PHY configuration parameter on the Main tab.
• You select the value of Full Duplex for the Duplex mode parameter on the Main tab.
Parameter Type Range Default
Setting
Parameter Description
KR4 General Options
Enable KR4 Boolean • True
• False
False If this parameter is turned on, the IP core is a
40GBASE-KR4 variation. If this parameter is turned
off, the IP core is not a 40GBASE-KR4 variation, and
the other parameters on this tab are not available.
Enable KR4
Reconfigura‐
tion
Boolean • True
• False
True If this parameter is turned on, the IP core supports
dynamic analog reconfiguration through a dedicated
reconfiguration interface. If this parameter is turned
off, the IP core cannot support auto-negotiation (AN)
or link training (LT) modes, and the AN and LT
parameters on this tab are not available. This
parameter does not affect FEC availability.
Auto-Negotiation
Enable Auto-
Negotiation
Boolean • True
• False
True If this parameter is turned on, the IP core includes
logic to implement auto-negotiation as defined in
Clause 73 of IEEE Std 802.3ap–2007. If this parameter
is turned off, the IP core does not include auto-
negotiation logic and cannot perform auto-negotia‐
tion.
Currently the IP core can only negotiate to KR4
mode.
Link fail inhibit
time for 40Gb
Ethernet
Integer
(Unit:
ms)
500–510
ms
504 ms Specifies the time before link_status is set to FAIL
or OK. A link fails if the time duration specified by
this parameter expires before link_status is set to
OK. For more information, refer to Clause 73 Auto-
Negotiation for Backplane Ethernet in IEEE Standard
802.3ap–2007.
The 40GBASE-KR4 IP core asserts the lanes_
deskewed signal to indicate link_status is OK.
2-6
IP Core Parameters
UG-01088
2014.12.15
Altera Corporation
Getting Started
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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