Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuale Utente Pagina 154
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• 40-100GbE IP Core Preamble Processing on page 3-21
Describes the RX preamble pass-through feature and the effect of bit [0] of the Preamble Pass-
Through Configuration register on IP core behavior.
• Inter-Packet Gap Generation and Insertion on page 3-5
Information about the effects of the IPG_DEL_PERIOD register and the IPG_DEL_ENABLE register on IP
core behavior.
MAC Address Registers
All MAC addresses are stored in 2 words of 24 bits (3 bytes) in natural reading order. For example, an
Altera Device ID of 00-07-ED-11-22-33 is stored with the more significant word set to 24’h0007ED and
the least significant word set to 24’h112233.
The following table describes the MAC address registers. Additional information about the MADDR_CTRL
register follows the table.
Table 3-46: MAC Address Registers
Address Name Bit Description HW Reset
Value
Access
0x140 MADDR_CTRL
[31] When set to 1, the source address is
Inserted in TX packets.
1’b0 RW
[30] When set to 1, enables the IP core to
check the destination address in RX
packets. When set to 0, all RX packets
are considered to have a matching
destination address.
If you enable destination address
filtering, by setting bit 0 of the RX_
FILTER_CTRL register (offset 0x103)
to the value of 0, but this bit, bit 30 of
the MADDR_CTRL register, is also set to
the value of 0, the IP core considers
all destination addresses to match.
1’b0 RW
[29:1] Reserved. 0x0000000
0
[0] When set to 1, enables destination
address 0x160-0x161 checking. If this
bit has the value of 0 and bit 30 has
the value of 1, the IP core considers
all destination addresses to not
match.
1’b0 RW
0x141 SRC_AD_LO [23:0] Source address (lower 24 bits). 0x00FF1234 RW
0x142 SRC_AD_HI [23:0] Source address (upper 24 bits). 0x000007ED RW
UG-01088
2014.12.15
MAC Address Registers
3-107
Functional Description
Altera Corporation
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- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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