Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuale Utente Pagina 163
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Address Name- Description Access
0x2B7 Reserved
0x2B8 CNTR_RX_FCS Number of received packets with FCS errors. This register
maintains a count of the number of pulses on the l<n>_rx_
fcs_error output signal in variations with a custom
streaming client interface (variations without adapters).
RO
Related Information
• Statistics Counters Interface on page 3-39
• MAC Configuration and Filter Registers on page 3-99
For more information about the MAC_CMD_config register.
40‑100GbE Example Design Registers
The following sections describe the registers that are included in the 40-100GbE example design and are
not a part of the 40-100GbE IP core. These registers are not available in the example designs for the
40GBASE-KR4 IP core variations.
PMD Registers on page 3-116
MDIO Registers on page 3-117
2-Wire Serial Interface Registers on page 3-118
Related Information
40-100GbE IP Core Example Design on page 5-1
Altera provides an example design with the 40-100GbE IP core. This example design is ready for
compilation and can be configured on a target device. The listed registers are part of the example design.
PMD Registers
Table 3-50: PMD Control and Status Registers
The physical medium dependent (PMD) control and status registers allow you to turn on and determine the status
of the PMD device in the 40-100GbE IP core example design.
Address Name Bits Description HW Reset Value Access
0x400 PMD_VERSION [31:0] PMD revision. The character string is
“OPTs.”
0x4F505473 R
0x401 SCRATCH_PMD [31:0] Scratch register available for testing. 0x00000000 RW
0x402 PMD_CMD_
CONFIG
[0] Writing a 1 enables the PMD. When
you set this register to the value of 1,
the IP core seeks RX lock.
0x00000000 RW
3-116
40‑100GbE Example Design Registers
UG-01088
2014.12.15
Altera Corporation
Functional Description
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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