Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuale Utente Pagina 192
- Pagina / 199
- Indice
- SEGNALIBRI
Valutato. / 5. Basato su recensioni clienti
Date ACDS
Version
Changes
• In "Simulating the 40-100GbE IP Core with the Testbenches" section,
removed option to include or exclude waveform generation in the
simulation scripts. The scripts do include this option in pre-13.1
releases.
• Corrected topics to include links to both internal (other sections) and
external (other documents and websites). Previously only one or the
other appeared in each section in the document.
• Fixed assorted typos.
November
2013
v13.1
(2013.11.04
)
• Added new 40GBASE-KR4 support with FEC option, including new
parameters, signals, registers, testbench, and example design.
• Added new parameter for Synchronous Ethernet support option to
separate the reference input clocks for the RX CDR PLL and the TX PLL
and make the RX recovered clock visible.
• Added the following new signals:
• Link fault signals visible in duplex variations: remote_fault_status
and local_fault_status.
• PHY status signals visible in MAC+PHY variations: tx_lanes_
stable and lanes_deskewed.
• New clock signals for SyncE variations: rx_clk_ref, tx_clk_ref,
and rx_recovered_clk.
• New 40GBASE-KR4 signals for analog reconfiguration.
• Updated testbench descriptions to describe the new streamlined
testbenches and the new 40GBASE-KR4 example design and testbench.
• Updated descriptions of testbenches and example designs to clarify the
user no longer needs to configure the DUT with a specific name and
clock rate.
• Updated resource utilization numbers.
• Corrected module names in 40GbE IP core resource utilization tables.
July 2013 1.3(v13.0) • Corrected signal widths and descriptions in Figure 3-2 on page 3-2 and
Figure 3-3 on page 3-3.
• Corrected Avalon-ST client interface signal widths in Figure 3-5 on page
3-8, Table 3-2 on page 3-8, Figure 3-20 on page 3-23, and Table 3-6 on
page 3-23.
• Renamed and reorganized "Signals" on page 3-40.
UG-01088
2014.12.15
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision
History
D-3
Additional Information
Altera Corporation
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
Prodotti e manuali riguardandi Strumenti di misura Altera 40-Gbps Ethernet MAC and PHY MegaCore Function
(39 pagine)© 2020, manymanuals.it. Tutti i diritti riservati | 0.028 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commenti su questo manuale