Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuale Utente Pagina 56
- Pagina / 199
- Indice
- SEGNALIBRI
Valutato. / 5. Basato su recensioni clienti
Figure 3-5: Traffic on the TX and RX Client Interface for 100GbE IP Core Using the Eight- to Five-Word
Adapters
Shows typical traffic for the TX and RX Avalon-ST interface of the 100GbE IP core. This example shows a
part of a ModelSim simulation of the parallel testbench provided with the IP core.
l8_tx_data[511:0]
l8_tx_startofpacket
l8_tx_endofpacket
l8_tx_empty[5:0]
l8_tx_ready
l8_tx_valid
l8_rx_data[511:0]
l8_rx_startofpacket
l8_rx_endofpacket
l8_rx_empty[5:0]
l8_rx_valid
l8_rx_error
.. . . . . . . . .
7CD901437CD901427C
. . . . . . . .
3BCA01273BCA01263BCA01253
. . . . .
00 2F 00 29 00
64
..
64
. .
A
. .
A
.
A
. .
A
. .
6
. .
6
. .
6E
.
6
.
07
. .
FF
. .
FF
.
07
. .
FD4
. .
0707070707070
30
.
30 10 30
.
22 02 22 0D 2E 0E
.
05
.
Related Information
• Testbenches with Adapters on page 2-15
Describes the 40GbE example in detail.
• Avalon Interface Specifications
For more information about the Avalon-ST interface.
40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface)
When no adapters are used, the 40GbE custom interface bus width is 2 words (128 bits) and the 100GbE
custom interface bus width is 5 words (320 bits). In both cases the client interfaces operate at a frequency
above 315 MHz.
Figure 3-6: TX Client to MAC Interface Without Adapters
The custom streaming interface bus width varies with the IP core variation. In the figure, <w> = 2 for the
40GbE IP core and <w> = 5 for the 100GbE IP core.
TX Client
Logic
din[<w>*64-1:0]
din_start[<w>-1:0]
din_end_pos[<w>*8-1:0]
din_ack
TX MAC
clk_txmac
UG-01088
2014.12.15
40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface)
3-9
Functional Description
Altera Corporation
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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