Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuale Utente Pagina 69
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By default, the MAC RX removes all Start, SFD, preamble, and IPG bytes from accepted frames. However,
if you turn on the RX preamble pass-through feature, by setting bit 0 of the Preamble Pass-Through
Configuration register at offset 0x125, the MAC RX does not remove the eight-byte preamble sequence.
Related Information
MAC Feature Configuration Registers on page 3-105
Information about the Preamble Pass-Through Configuration register.
40-100GbE IP Core FCS (CRC-32) Removal
Independent user configuration register bits control FCS CRC removal at runtime. CRC removal supports
both narrow and wide bus options. Bit 1 of the CRC_CONFIG register enables and disables CRC removal; by
default, CRC removal is enabled.
In the user interface, the EOP signal (l<n>_rx_endofpacket or dout_last_data) indicates the end of
CRC data if CRC is not removed. When CRC is removed, the EOP signal indicates the final byte of
payload.
By default, the IP core asserts the FCS error signal (l<n>_rx_fcs_error or dout_fcs_error) and the
EOP signal on the same clock cycle if the current frame has an FCS error. However, if the IP core is in RX
automatic pad removal mode, the signals might not be asserted in the same clock cycle.
Related Information
RX Automatic Pad Removal Control on page 3-22
40-100GbE IP Core CRC Checking
The 32-bit CRC field is received in the order: X32, X30, . . . X1, and X0 , where X32 is the most significant
bit of the FCS field and occupies the least significant bit position in the first FCS byte.
If a CRC32 error is detected, the RX MAC marks the frame invalid by asserting the dout_fcs_error and
dout_fcs_valid signals.
When operating in the cut-through or store and forward mode, with Avalon–ST or the custom streaming
client interface, the FCS result is always preserved.
RX CRC Forwarding
The CRC-32 field is forwarded to the client interface after the final byte of data, if the CRC removal
option is not enabled.
Related Information
40-100GbE IP Core FCS (CRC-32) Removal on page 3-22
RX Automatic Pad Removal Control
In the 40GbE and 100GbE MAC configurations, you can enable and disable RX automatic pad removal
with a configuration register bit in run-time.
The following figures illustrate the normal format of received data at the MAC RX interface.
3-22
40-100GbE IP Core FCS (CRC-32) Removal
UG-01088
2014.12.15
Altera Corporation
Functional Description
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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