Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuale Utente Pagina 29
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Parameter Type Range Default
Setting
Parameter Description
Auto-Negotia‐
tion Master
String • Lane 0
• Lane 1
• Lane 2
• Lane 3
Lane 0 Selects the master channel for auto-negotiation.
Pause ability–
C0
Boolean • True
• False
True If this parameter is turned on, the IP core supports
symmetric pauses as defined in Annex 28B of Section
2 of IEEE Std 802.3–2008.
Pause ability–
C1
Boolean • True
• False
True If this parameter is turned on, the IP core supports
asymmetric pauses as defined in Annex 28B of
Section 2 of IEEE Std 802.3–2008.
Link Training: PMA Parameters
VMAXRULE Integer
0–63 60
Specifies the maximum V
OD
. The default value, 60,
represents 1200 mV.
VMINRULE Integer
0–63 9
Specifies the minimum V
OD
. The default value, 9,
represents 165 mV.
VODMINRULE Integer
0–63 24
Specifies the minimum V
OD
for the first tap. The
default value, 24, represents 440 mV.
VPOSTRULE Integer
0–31 31
Specifies the maximum value that the internal
algorithm for pre-emphasis will ever test in
determining the optimum post-tap setting.
VPRERULE Integer
0–15 15
Specifies the maximum value that the internal
algorithm for pre-emphasis will ever test in
determining the optimum pre-tap setting.
PREMAINVAL Integer
0–63 60
Specifies the Preset V
OD
value. This value is set by the
Preset command of the link training protocol,
defined in Clause 72.6.10.2.3.1 of IEEE Std 802.3ap–
2007.
PREPOSTVAL Integer
0–31 0
Specifies the preset Post-tap value.
PREPREVAL Integer
0–15 0
Specifies the preset Pre-tap value.
INITMAINVAL Integer
0–63 52
Specifies the initial V
OD
value. This value is set by the
Initialize command of the link training protocol,
defined in Clause 72.6.10.2.3.2 of IEEE Std 802.3ap–
2007.
INITPOSTVAL Integer
0–31 30
Specifies the initial Post-tap value.
UG-01088
2014.12.15
IP Core Parameters
2-7
Getting Started
Altera Corporation
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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