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Signal Name Direction Description
dout_runt_last_
data[<w>-1:0]
Output Indicates that the last_data (the final data byte of the frame) is the final
data byte of a runt frame (< 64 bytes). If a frame is eight bytes or
smaller, it is considered a decoding error and not a runt frame, and the
IP core does not flag it with this signal.
dout_payload[<w>
-1:0]
Output Word contains packet data (including destination and source
addresses) as opposed to only containing Idle bytes. CRC and padding
bits are considered data for this signal. When preamble pass-through is
turned on, the preamble is also considered data for this signal.
dout_fcs_error
Output The current or most recent last_data byte is part of a frame with an
incorrect FCS (CRC-32) value. By default, the IP core asserts dout_
fcs_error in the same cycle as the dout_last_data signal. However,
in RX automatic pad removal mode, the dout_fcs_error signal might
lag the dout_last_data signal for the frame.
dout_fcs_valid
Output The FCS error bit is valid.
dout_dst_addr_
match[<w>-1:0]
Output The first data word in a frame that matches the destination address in
the DST_AD0_LO and DST_AD0_HI registers. However, if bit 30 of the
MADDR_CTRL register has the value of 0, the address is always considered
to match. Otherwise, if bit 0 of the MADDR_CTRL register has the value of
0, the address is always considered to not match.
dout_valid
Output The dout_d bus contents are valid. This signal is occasionally
deasserted due to clock crossing.
clk_rxmac
Input RX MAC clock. The minimum clock frequency is 315 MHz. The clk_
rxmac clock and the clk_txmac clock (which clocks the TX datapath)
are not related and their rates do not have to match.
The data bytes use 100 Gigabit Media Independent Interface (CGMII-like) encoding. For packet payload
bytes, the dout_c bit is set to 0 and the dout_d byte is the packet data. You can use this information to
transmit out-of-spec data such as customized preambles when implementing non-standard variants of the
IEEE 802.3ba-2010 100G Ethernet Standard. If the additional customized data is not required, simply
ignore all words which are marked with dout_payload = 0 and discard the dout_c bus.
In RX preamble pass-through mode, dout_c has the value of 1 while the start byte of the preamble is
presented on the RX interface, and dout_c has the value of 0 while the remainder of the preamble
sequence (six-byte preamble plus SFD byte) is presented on the RX interface. While the preamble
sequence is presented on the RX interface, dout_payload has the value of 1.
Related Information
• RX Automatic Pad Removal Control on page 3-22
Information about the automatic pad removal mode and its effect on the dout_fcs_error signal.
• MAC Address Registers on page 3-107
Additional information about the MADDR_CTRL, DST_AD0_LO, and DST_AD0_HI address registers and
how various register settings interact to affect the value of the dout_dst_addr_match signal.
UG-01088
2014.12.15
40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3-29
Functional Description
Altera Corporation
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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