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Table 6-6: Hardware Demonstration Files
Files are named with <prefix>_<name>.<extension> where <prefix> represents the device (av for Arria V devices,
cv for Cyclone V devices, and sv for Stratix V devices).
File Type File Description
Verilog HDL
design files
top.v
Top-level design file.
bitec_reconfig_alt_<prefix>.v Reconfiguration manager top-level. This
module is a high-level FSM that generates the
control signals to reconfigure the VOD and
pre-emphasis, selects the PLL reference clock,
and reconfigures clock divider setting. It loops
through all the channels and transceiver
settings.
altera_pll_reconfig_core.v
altera_pll_reconfig_mif_reader.v
altera_pll_reconfig_top.v
bitec_cc_fifo.v
bitec_cc_pulse.v
bitec_clkrev.v
bitec_fpll_cntrl.v
bitec_fpll_reconf.v
bitec_loop_cntrl.v
bitec_vsyncgen.v
clkrec_pll_<prefix>.v
Clock recovery core encrypted design files.
IP Catalog files video_pll<prefix>.v
pll_135.v
gxb_reconfig.v
gxb_reset.v
gxb_rx.v
gxb_tx.v
IP Catalog variants for the various helper IP
cores.
Qsys system control.qsys Qsys system file.
6-24
Copy the Design Files to Your Working Directory
UG-01131
2015.05.04
Altera Corporation
DisplayPort IP Core Hardware Demonstration
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Item Description 10
- Related Information 10
- About This IP Core 11
- Device Family Support 12
- IP Core Verification 12
- Getting Started 14
- Simulating the Design 15
- DisplayPort Source 17
- Source Functional Description 18
- Main Data Path 19
- Packetizer Path 20
- Measurement Path 20
- Blank Generator Path 20
- Multiplexer 20
- Source Parameters 21
- Parameter Description 22
- Source Interfaces 23
- Interface Signal Type Clock 26
- Port Direction Description 26
- Controller Interface 27
- AUX Interface 28
- Video Interface 28
- TX Transceiver Interface 29
- Secondary Stream Interface 30
- Audio Interface 32
- 7 B3 0 7 B2 0 7 B1 0 7 B0 0 33
- 31 24 23 16 15 8 7 0 33
- SP R PR P C U V 33
- 31 29 28 25 2430 27 26 23 0 33
- MSA Interface 34
- Source Clock Tree 35
- DisplayPort Sink 37
- Transceiver Management 38
- Sink Parameters 40
- Sink Interfaces 42
- Interface Port Type Clock 48
- Debugging Interface 50
- Bit Comments 51
- Clocked Video Input Interface 54
- RX Transceiver Interface 55
- Bit Signal Comments 59
- Sink Clock Tree 60
- Figure 5-11: Sink Clock Tree 61
- Subscribe 62
- FPGA Development Board 63
- Clock Recovery Core 65
- Clock Recovery Interface 67
- Video Input Port 71
- Transceiver and Clocking 72
- Datapath Options 73
- Standard PCS 74
- Required Hardware 75
- Description 77
- HSMC Connector J4A 77
- HSMC Connector J4B 78
- HSMC Connector J4C 80
- DP RX Connector J1 80
- DP RX Connector J2 81
- Design Walkthrough 83
- Set Up the Hardware 84
- File Type File Description 85
- Build the FPGA Design 86
- Load, and Run the Software 86
- View the Results 87
- Altera Corporation 100
- Send Feedback 100
- DisplayPort API Reference 102
- UG-01131 103
- 2015.05.04 103
- Locations 122
- Bit Bit Name Function 123
- DPTX_TX_STATUS 124
- Source MSA Registers 125
- DPTX0_MSA_VTOTAL 126
- DPTX0_MSA_HSP 126
- DPTX0_MSA_HSW 126
- DPTX0_MSA_HSTART 127
- DPTX0_MSA_VSTART 127
- DPTX0_MSA_VSP 127
- DPTX0_MSA_VSW 128
- DPTX0_MSA_HWIDTH 128
- DPTX0_MSA_VHEIGHT 128
- DPTX0_MSA_MISC0 129
- DPTX0_MSA_MISC1 129
- DPTX0_MSA_COLOUR 129
- DPTX_PRE_VOLT0 130
- DPTX_PRE_VOLT1 131
- DPTX_PRE_VOLT2 131
- DPTX_PRE_VOLT3 131
- Source Timestamp 132
- Source Audio Registers 133
- Source CRC Registers 134
- Source MST Registers 135
- DPTX_MST_VCPTAB0 136
- DPTX_MST_VCPTAB1 136
- DPTX_MST_VCPTAB2 137
- DPTX_MST_VCPTAB3 138
- DPTX_MST_VCPTAB4 138
- DPTX_MST_VCPTAB5 139
- DPTX_MST_VCPTAB6 139
- DPTX_MST_VCPTAB7 140
- DPTX_MST_TAVG_TS 141
- DPTX_AUX_CONTROL 141
- DPTX_AUX_CMD 142
- DPTX_AUX_BYTE0 143
- DPTX_AUX_BYTE1 143
- DPTX_AUX_BYTE2 143
- DPTX_AUX_BYTE3 144
- DPTX_AUX_BYTE4 144
- DPTX_AUX_BYTE5 144
- DPTX_AUX_BYTE6 145
- DPTX_AUX_BYTE7 145
- DPTX_AUX_BYTE8 145
- DPTX_AUX_BYTE9 146
- DPTX_AUX_BYTE10 146
- DPTX_AUX_BYTE11 146
- DPTX_AUX_BYTE12 147
- DPTX_AUX_BYTE13 147
- DPTX_AUX_BYTE14 148
- DPTX_AUX_BYTE15 148
- DPTX_AUX_BYTE16 148
- DPTX_AUX_BYTE17 149
- DPTX_AUX_BYTE18 149
- DPTX_AUX_RESET 149
- Location Name Address 150
- DPRX_RX_STATUS 154
- DPRX_BER_CONTROL 156
- Sink Timestamp 158
- Sink Bit-Error Counters 158
- Sink MSA Registers 159
- DPRX0_MSA_MVID 160
- DPRX0_MSA_NVID 160
- DPRX0_MSA_HTOTAL 160
- DPRX0_MSA_VTOTAL 160
- DPRX0_MSA_HSP 161
- DPRX0_MSA_HSW 161
- DPRX0_MSA_HSTART 161
- DPRX0_MSA_VSTART 162
- DPRX0_MSA_VSP 162
- DPRX0_MSA_VSW 162
- DPRX0_MSA_HWIDTH 163
- DPRX0_MSA_VHEIGHT 163
- DPRX0_MSA_MISC0 163
- DPRX0_MSA_MISC1 164
- DPRX0_VBID 164
- Sink Audio Registers 165
- DPRX0_AUD_AIF1 166
- DPRX0_AUD_AIF2 166
- DPRX0_AUD_AIF3 166
- Sink MST Registers 167
- DPRX_MST_VCPTAB0 168
- DPRX_MST_VCPTAB1 169
- DPRX_MST_VCPTAB3 170
- DPRX_MST_VCPTAB2 170
- DPRX_MST_VCPTAB4 171
- DPRX_MST_VCPTAB5 171
- DPRX_MST_VCPTAB6 172
- Sink AUX Controller Interface 173
- DPRX_AUX_STATUS 174
- DPRX_AUX_COMMAND 175
- DPRX_AUX_BYTE0 175
- DPRX_AUX_BYTE1 176
- DPRX_AUX_BYTE2 176
- DPRX_AUX_BYTE3 176
- DPRX_AUX_BYTE4 177
- DPRX_AUX_BYTE5 177
- DPRX_AUX_BYTE6 177
- DPRX_AUX_BYTE7 178
- DPRX_AUX_BYTE8 178
- DPRX_AUX_BYTE9 178
- DPRX_AUX_BYTE10 179
- DPRX_AUX_BYTE11 179
- DPRX_AUX_BYTE12 180
- DPRX_AUX_BYTE13 180
- DPRX_AUX_BYTE14 180
- DPRX_AUX_BYTE15 181
- DPRX_AUX_BYTE16 181
- DPRX_AUX_BYTE17 181
- DPRX_AUX_BYTE18 182
- DPRX_AUX_I2C0 182
- DPRX_AUX_I2C1 182
- DPRX_AUX_RESET 183
- DPRX_AUX_HPD 183
- Sink-Supported DPCD Locations 184
- Location Name Address Without 185
- Controller 185
- With Controller 185
- 0×200D — Yes 190
- 0×200E — Yes 190
- 0×200F — Yes 190
- Additional Information 191
- Date Version Changes 192
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