Altera DisplayPort MegaCore Function Manuale Utente Scaricare il pdf (Pagina 30)

reset (tx_digitalreset), analog reset (tx_analogreset), and PLL powerdown signals

(tx_pll_powerdown) of the transceiver.

Transceiver Reconfiguration Interface

You can reconfigure the transceiver to accept single reference clock. The single reference clock is a 135-

MHz clock for all bit rates: RBR, HBR, and HBR2.

• During run-time, you can reconfigure the transceiver to operate in either one of the bit rate by

changing TX CMU PLL divide ratio.

When the IP core makes a request, the tx_reconfig_req port goes high. The user logic asserts

tx_reconfig_ack and then reconfigures the transceiver. During reconfiguration, the user logic holds

tx_reconfig_busy high. The user logic drives it low when reconfiguration completes.

Note: The transceiver requires a reconfiguration controller. Reset the transceiver to a default state upon

power-up.

Related Information

• AN 645: Dynamic Reconfiguration of PMA Controls in Stratix V Devices

Provides more information about using the Transceiver Reconfiguration Controller to reconfigure the

Stratix V Physical Media Attachment (PMA) controls dynamically.

• Altera Transceiver PHY IP Core User Guide

Provides more information about how to reconfigure the transceiver for 28-nm devices.

• AN 676: Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in

Arria V and Cyclone V Devices

Provides more information about using the Transceiver Reconfiguration Controller to reconfigure the

Arria V Physical Media Attachment (PMA) controls dynamically.

• AN 678: High-Speed Link Tuning Using Signal Conditioning Circuitry

Provides more information about link tuning.

• Arria 10 Transceiver PHY User Guide

Provides more information about how to reconfigure the transceiver for Arria 10 devices.

Transceiver Analog Reconfiguration Interface

The tx_analog_reconfig interface uses the tx_vod and tx_emp transceiver management control ports.

You must map these ports for the device you are using. To change these values, the core drives

tx_analog_reconfig_req high. Then, the user logic sets tx_analog_reconfig_ack high to acknowledge

and drives tx_analog_reconfig_busy high during reconfiguration. When reconfiguration completes,

the user logic drives tx_analog_reconfig_busy low.

Secondary Stream Interface

You can transmit the secondary stream data over the DisplayPort main link through the secondary stream

(txN_ss) interface. This interface uses handshaking and back pressure to control packet delivery.

Internally, the core uses a FIFO to store packets until a slot becomes available on the main link. If the

FIFO fills up, the secondary stream interface stops accepting packets and applies back pressure. The

packet must be available at the time of sending because the txN_ss port does not support forward

pressure.

4-14

Transceiver Reconfiguration Interface

UG-01131

2015.05.04

Altera Corporation

DisplayPort Source

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