Altera Avalon Verification IP Suite Manuale Utente Scaricare il pdf (Pagina 80)

set_enable_a_constant_during_clk_disabled()

set_enable_a_constant_during_clk_disabled()Prototype:

Verilog HDL: Boolean

VHDL: N.A.

Arguments:

voidReturns:

Enables an assertion that ensures that all signals are held constant if clken

is deasserted.

Description:

Verilog HDLLanguage support:

set_enable_a_constant_during_waitrequest()

set_enable_a_constant_during_waitrequest()Prototype:

Verilog HDL: Boolean

VHDL: N.A.

Arguments:

voidReturns:

Enables an assertion ensuring read, write, writedata, address,

burstcount, and byteenable are held constant if waitrequest is asserted.

Disabled when waitrequest is not supported.

Description:

Verilog HDLLanguage support:

set_enable_a_exclusive_read_write()

set_enable_a_exclusive_read_write()Prototype:

Verilog HDL: Boolean

VHDL: N.A.

Arguments:

voidReturns:

Enables an assertion that ensures read and write are not asserted simulta-

neously. Disabled when either read or write is not supported.

Description:

Verilog HDLLanguage support:

Avalon-MM Monitor

Altera Corporation

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set_enable_a_constant_during_clk_disabled()

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Altera Avalon Verification IP Suite Manuale Utente Pagina 80