Altera Avalon Verification IP Suite Manuale Utente

Introduction to Avalon Verification IP SuiteUser Guide101 Innovation DriveSan Jose, CA 95134www.altera.comUG-010732014.06.30SubscribeSend Feedback

event_instruction_inconsistent() ...15-3event_instruction

get_command_data()bit [AV_DATA_W-1:0] get_command_data(int index)Prototype:Verilog HDL: indexVHDL: command_data, index, bfm_id, req_if(bfm_id)Argument

get_command_queue_size()int get_command_queue_size()Prototype:Verilog HDL: NoneVHDL: command_queue_size, bfm_id, req_if(bfm_id)Arguments:intReturns:Qu

get_command_transaction_id()AvalonTransactionId_t get_command_transaction_id()Prototype:Verilog HDL: NoneVHDL: command_transaction_id, bfm_id, req_if(

get_response_address()bit [AV_ADDRESS_W-1:0] get_response_address()Prototype:Verilog HDL: NoneVHDL: response_address, bfm_id, req_if(bfm_id)Arguments:

get_response_data()bit [AV_DATA_W-1:0] get_response_data(int index)Prototype:Verilog HDL: indexVHDL: response_data, index, bfm_id, req_if(bfm_id)Argum

get_response_read_id()AvalonTransactionId_t get_response_read_id()Prototype:Verilog HDL: NoneVHDL: response_read_id, bfm_id, req_if(bfm_id)Arguments:A

get_response_wait_time()int get_response_wait_time(int index)Prototype:Verilog HDL: indexVHDL: response_wait_time, index, bfm_id, req_if(bfm_id)Argume

get_transaction_fifo_max()int get_transaction_fifo_max()Prototype:Verilog HDL: NoneVHDL: transaction_fifo_max, bfm_id, req_if(bfm_id)Arguments:intRetu

init()init()Prototype:Verilog HDL: NoneVHDL: bfm_id, req_if(bfm_id)Arguments:voidReturns:Initializes the counters and clears the queue.Description:Ver

set_command_transaction_mode()set_command_transaction_mode()Prototype:Verilog HDL: int modeVHDL: int mode, bfm_id, req_if(bfm_id)Arguments:voidReturns

Running the Simulation ...16-5Observing th

signal_command_receivedsignal_command_receivedPrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Notifies the testbench that a command was det

signal_response_completesignal_response_completePrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Triggers when either signal_read_response_c

signal_write_response_completesignal_write_response_completePrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Notifies the testbench that the

8Avalon-ST Source BFMSubscribeSend FeedbackThe Avalon-ST Source BFM implements the Avalon-ST interface protocol. The Avalon-ST protocol ispoint-to-poi

Figure 8-2: Avalon-ST Source Sending Data to a SinkThe following figure illustrates the timing when READY_LATENCY = 0.CLKreadyvaliddataD1 D2Ssrc_drSsr

• Response Descriptor—Collects information about completed transactions.Figure 8-3: Block Diagram of the Avalon-ST Source BFMTransaction DescriptorPub

DescriptionLegalValuesDefaultValueParameterPort WidthsData symbol width in bits. The symbol width shouldbe 8 for byte-oriented interfaces.1–10248Symbo

event_min_transaction_queue_size()event_min_transaction_queue_size()Prototype:Verilog HDL: N.A.VHDL: bfm_idArguments:voidReturns:Notifies the testbenc

event_src_ready()event_src_ready()Prototype:Verilog HDL: N.A.VHDL: bfm_idArguments:voidReturns:Notifies the testbench that the ready signal was assert

get_response_queue_size()get_response_queue_size()Prototype:Verilog HDL: NoneVHDL: response_queue_size, bfm_id, req_if(bfm_id)Arguments:intReturns:Ret

1Introduction to Avalon Verification IP SuiteSubscribeSend FeedbackThe Avalon®Verification IP Suite provides bus functional models (BFMs) to simulate

get_version()get_version()Prototype:Verilog HDL: NoneVHDL: N.A.Arguments:StringReturns:Returns BFM version as a string of three integers separated by

push_transaction()push_transaction()Prototype:Verilog HDL: NoneVHDL: bfm_id, req_if(bfm_id)Arguments:voidReturns:Inserts the out-going transaction int

set_response_timeout()set_response_timeout(int cycles)Prototype:Verilog HDL: cyclesVHDL: cycles, bfm_id, req_if(bfm_id)Arguments:voidReturns:Sets the

set_transaction_idles()set_transaction_idles(bit[31:0] idle_cycles)Prototype:Verilog HDL: idle_cyclesVHDL: idle_cycles, bfm_id, req_if(bfm_id)Argument

set_transaction_sop()set_transaction_sop(bit sop)Prototype:Verilog HDL: sopVHDL: sop, bfm_id, req_if(bfm_id)Arguments:voidReturns:Sets the status of t

signal_response_donesignal_response_donePrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Signals that the response to a driven data beat is

signal_src_transaction_completesignal_src_transaction_completePrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Signals that all pending tran

9Avalon-ST Sink BFMSubscribeSend FeedbackThe Avalon-ST Sink BFM implements the Avalon-ST interface protocol. The Avalon-ST protocol ispoint-to-point,

Figure 9-2: Avalon-ST Source and Sink TimingCLKreadyvaliddataD1 D2Ssnk_rdyaSsnk_rdydSsnk_rdydStrSsnk_rdyaTidleTidleTable 9-1: Key to AnnotationsThe fo

• Public Events—Signals the events described in the API.Figure 9-3: Block Diagram of the Avalon-ST Sink BFMTransaction DescriptorPublicEventsAvalon-ST

Verilog HDL with a few basic SystemVerilog constructs that are supported by ModelSim®-Altera Edition(AE).The Quartus II software version 13.0 and high

DescriptionLegalValuesDefaultValueParameterPort WidthsData symbol width in bits. The symbol width shouldbe 8 for byte-oriented interfaces.1–10248Symbo

event_sink_ready_assert()event_sink_ready_assert()Prototype:Verilog HDL: N.A.VHDL: bfm_idArguments:voidReturns:Signals that the ready signal was asser

get_transaction_idles()get_transaction_idles()Prototype:Verilog HDL: NoneVHDL: transaction_idles,bfm_id, req_if(bfm_id)Arguments:bit[31:0]Returns:Retu

get_transaction_error()get_transaction_error()Prototype:Verilog HDL: NoneVHDL: transaction_error, bfm_id, req_if(bfm_id)Arguments:STError_tReturns:Ret

get_version()get_version()Prototype:Verilog HDL: NoneVHDL: N.A.Arguments:stringReturns:Returns BFM version as a string of three integers separated by

set_ready()set_ready()Prototype:Verilog HDL: read_bitVHDL: read_bit, bfm_id, req_if(bfm_id)Arguments:voidReturns:Sets the value of the interface’s rea

signal_sink_ready_deassertsignal_sink_ready_deassertPrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Signals that sink_ready is deasserted,

10Avalon-ST MonitorSubscribeSend FeedbackThe Avalon-ST Monitor verifies Avalon-ST interfaces using SystemVerilog assertions. In addition, it providest

ParametersThe Avalon-ST monitor supports the full range of signals defined for the Avalon-ST source and sink interfaces.You can customize the Avalon-S

Avalon-ST Monitor Assertion Checking APIAssertion checking methods enable and disable protocol assertions to ensure protocol compliance. Forexample, t

• API communication interface—Bridges the VHDL API to the API handler logic.Figure 1-1: VHDL Component BFMAPIInteractionBFM InterfaceVHDL BFMCommunica

set_enable_a_no_data_outside_packet()set_enable_a_no_data_outside_packet()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables an ass

set_enable_a_valid_legal()set_enable_a_valid_legal()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables an assertion that ensures va

set_enable_c_all_valid_beats()set_enable_c_all_valid_beats()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables a coverage point tha

set_enable_c_b2b_packet_different_channel()set_enable_c_b2b_packet_different_channel()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:En

set_enable_c_b2b_packet_within_single_cycle()set_enable_c_b2b_packet_within_single_cycle()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturn

set_enable_c_error()set_enable_c_error()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables a coverage point that ensures test cover

set_enable_c_multiple_packet_per_cycle()set_enable_c_multiple_packet_per_cycle()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables

set_enable_c_packet()set_enable_c_packet()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables a coverage point that ensures test cov

set_enable_c_packet_with_back_pressure()set_enable_c_packet_with_back_pressure()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables

set_enable_c_single_packet_per_cycle()set_enable_c_single_packet_per_cycle()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables a co

Figure 1-2: Avalon Verification IP Suite Testbench for Avalon-MM and Avalon-ST InterfacesTestbenchTest ProgramTraditional Verilog ImplementationORAval

set_enable_c_valid_non_ready()set_enable_c_valid_non_ready()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables a coverage point tha

event_transaction_fifo_overflow()event_transaction_fifo_overflow()Prototype:Verilog HDL: N.A.VHDL: bfm_idArguments:voidReturns:Notifies the testbench

get_transaction_eop()get_transaction_eop()Prototype:Verilog HDL: NoneVHDL: transaction_eop, bfm_id, req_if(bfm_id)Arguments:bit.Returns:Returns the tr

get_transaction_idles()get_transaction_idles()Prototype:Verilog HDL: NoneVHDL: transaction_idles, bfm_id, req_if(bfm_id)Arguments:bit[31:0].Returns:Re

pop_transaction()void pop_transaction()Prototype:Verilog HDL: NoneVHDL: bfm_id, req_if(bfm_id)Arguments:voidReturns:Removes the transaction descriptor

signal_fatal_errorsignal_fatal_errorPrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Notifies the testbench that a fatal error has occurred

11Conduit BFMSubscribeSend FeedbackYou can use Conduit BFMs to verify the following aspects of Avalon Conduit interfaces:• Port compatibility and pola

• A conduit port can also have a specific role named export. Ports with this role name are exported fromthe current system design module to the Condui

event_reset_assertedevent_reset_assertedPrototype:Verilog HDL: N.A.VHDL: NoneArguments:voidReturns:Notifies the testbench that reset has been asserted

set_<role name>()void set_<role name>()Prototype:Verilog HDL: new_valueVHDL: new_valueArguments:voidReturns:Rewrites the registers inside

2Clock Source BFMSubscribeSend FeedbackThe Avalon Verification IP Suite includes a Clock Source BFM that you can use to generate a clock signalfor you

12Tri-State Conduit BFMSubscribeSend FeedbackYou can use the Tri-State Conduit BFM to verify the following aspects of Avalon-TC interfaces:• Port comp

ParametersThe Tri-State Conduit BFM supports signals that interface to multiple external memory devices.Table 12-1: Tri-State Conduit BFM Parameter Se

event_interface_granted()event_interface_granted()Prototype:Verilog HDL: N.A.VHDL: NoneArguments:voidReturns:Notifies the testbench that the interface

event_min_transaction_queue_size()event_min_transaction_queue_size()Prototype:Verilog HDL: N.A.VHDL: NoneArguments:voidReturns:Notifies the testbench

get_transaction_latency()int get_transaction_latency()Prototype:Verilog HDL: NoneVHDL: latencyArguments:intReturns:Returns the latency field value fro

push_transaction()void push_transaction()Prototype:Verilog HDL: NoneVHDL: NoneArguments:voidReturns:Registers an output transaction into the BFM. All

set_num_of_transactions()int set_num_of_transactions()Prototype:Verilog HDL: multiple_transaction_numVHDL: multiple_transaction_numArguments:voidRetur

set_valid_transaction_<role name>_out()void set_valid_transaction_<role name>_out()Prototype:Verilog HDL: index, new_valueVHDL: index, new

signal_grant_deasserted_while_request_remain_assertedsignal_grant_deasserted_while_request_remain_assertedPrototype:Verilog HDL: NoneVHDL: N.A.Argumen

signal_min_transaction_queue_sizesignal_min_transaction_queue_sizePrototype:Verilog HDL: NoneVHDL: N.A.Arguments:None.Arguments:voidReturns:Triggers w

Clock_stop()clock_stop()Prototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Turns off the clock.Description:Verilog HDLLanguage support:get_run

13External Memory BFMSubscribeSend FeedbackYou can use external memory BFMs to verify the following aspects of external memory interfaces:• Read and w

DescriptionComponentCarries the shared address bus and data.Tri-State Conduit Pin SharerTri-State Conduit Inverse Pin SharerControls the external memo

DescriptionLegal ValuesDefault ValueOptionWhen On, the interface includes achipselect pin. When present, the slaveport ignores all Avalon-MM signals u

DescriptionLegal ValuesDefault ValueOptionSpecifies the conduit interface role name thatmatches the role name on the externalmemory device.N/Acdt_addr

External Memory BFM APIfill()fill()Prototype:VHDL:logic[DATA_W-1:0] databit[DATA_W-1:0] incrementbit[CDT_ADDRESS_W-1:0] address lowbit[CDT_ADDRESS_W-1

signal_api_callsignal_api_callPrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Triggers when a client make an API call.Description:Verilog H

14Nios II Custom Instruction Master BFMSubscribeSend FeedbackYou can use Nios II Custom Instruction Master BFM to verify the following aspects of the

The Nios II Custom Instruction Master BFM uses queues to manage instructions. You can use this BFM tomanage instructions in the following ways:• You c

DescriptionLegal ValuesDefaultValueOptionWhen On, the interface includes the readrb and b pins.On/OffOffUse Internal Register bWhen On, the interface

event_unexpected_result_received()event_unexpected_result_received()Prototype:Verilog HDL: N.A.VHDL: bfm_idArguments:voidReturns:Indicates that a resu

3Reset Source BFMSubscribeSend FeedbackThe Avalon Verification IP Suite includes a Reset Source BFM that you can use to generate a reset signal inyour

event_max_result_queue_size()event_max_result_queue_size()Prototype:Verilog HDL: N.A.VHDL: bfm_idArguments:voidReturns:Indicates that the received res

get_result_delay()int get_result_delay()Prototype:Verilog HDL: NoneVHDL: result_delay, bfm_id, req_if(bfm_id)Arguments:Width of the data (ci_data_t)th

get_version()string get_version()Prototype:Verilog HDL: NoneVHDL: N.A.Arguments:stringReturns:Returns the BFM version as a string of three integers se

pop_result()void pop_result()Prototype:Verilog HDL: NoneVHDL: bfm_id, req_if(bfm_id)Arguments:void.Returns:Removes the result instruction from the que

set_ci_clk_en()void set_ci_clk_en()Prototype:Verilog HDL: bit enableVHDL: bit enable, bfm_id, req_if(bfm_id)Arguments:voidReturns:Sets the ci_clk_en s

set_instruction_c()void set_instruction_c()Prototype:Verilog HDL: ci_addr_t addressVHDL: ci_addr_t address, bfm_id, req_if(bfm_id)Arguments:voidReturn

set_instruction_idle()void set_instruction_idle()Prototype:Verilog HDL: ci_data_t idleVHDL: ci_data_t idle, bfm_id, req_if(bfm_id)Arguments:voidReturn

set_instruction_timeout()void set_instruction_timeout()Prototype:Verilog HDL: int timeoutVHDL: int timeout, bfm_id, req_if(bfm_id)Arguments:voidReturn

set_min_instruction_queue_size()void set_min_instruction_queue_size(int size).Prototype:Verilog HDL: int sizeVHDL: int size, bfm_id, req_if(bfm_id)Arg

signal_fatal_errorsignal_fatal_errorPrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Notifies the testbench that a fatal error has occured i

reset_deassertreset_deassertPrototype:Verilog HDL: NoneVHDL: N.A.Arguments:void.Returns:Deasserts the reset signal.Description:Verilog HDLLanguage sup

signal_max_result_queue_sizesignal_max_result_queue_sizePrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Signals that the maximum pending re

15Nios II Custom Instruction Slave BFMSubscribeSend FeedbackYou can use Nios II Custom Instruction Slave BFM to verify the following aspects of the Ni

ParametersTable 15-1: Custom Instruction Slave BFM Parameter SettingsDescriptionLegal ValuesDefaultValueOptionGeneralSpecifies the number of operands

Nios II Custom Instruction Slave BFM APIevent_known_instruction_received()event_known_instruction_received()Prototype:Verilog HDL: N.A.VHDL: bfm_idArg

event_result_driven()event_result_driven()Prototype:Verilog HDL: N.A.VHDL: bfm_idArguments:voidReturns:Indicates that the result will be driven out fr

get_ci_clk_en()void get_ci_clk_en(bit enable)Prototype:Verilog HDL: NoneVHDL: clk_en, bfm_id, req_if(bfm_id)Arguments:bit enableReturns:Retrieves the

get_instruction_dataa()void get_instruction_dataa()Prototype:Verilog HDL: NoneVHDL: instruction_dataa, bfm_id, req_if(bfm_id)Arguments:ci_data_t dataR

get_instruction_readra()logic get_instruction_readra()Prototype:Verilog HDL: NoneVHDL: instruction_readra, bfm_id, req_if(bfm_id)Arguments:logicReturn

get_version()string get_version()Prototype:Verilog HDL: NoneVHDL: N.A.Arguments:stringReturns:Returns BFM version as a string of three integers separa

retrieve_instruction()void retrieve_instruction.Prototype:VHDL:output ci_data_t dataaVerilog HDL:output ci_data_t dataaArguments:output ci_data_t data

ContentsIntroduction to Avalon Verification IP Suite ...1-1Advantages of Using BFMs and Monitors ...

4Avalon Interrupt Source and Interrupt Sink BFMsSubscribeSend FeedbackThe Avalon Verification IP Suite includes Avalon Interrupt Source and Avalon Int

set_instruction_a()void set_instruction_a()Prototype:Verilog HDL: ci_addr_t addressVHDL: ci_addr_t address, bfm_id, req_if(bfm_id)Arguments:voidReturn

set_result_delay()void set_result_delay()Prototype:Verilog HDL: ci_data_t delayVHDL: ci_data_t delay, bfm_id, req_if(bfm_id)Arguments:voidReturns:Sets

signal_instructions_inconsistentsignal_instructions_inconsistentPrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Signals that an instruction

signal_result_drivensignal_result_drivenPrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Signals that a result has been driven from the slav

16Avalon-ST Verilog HDL TestbenchSubscribeSend FeedbackThis testbench shows how to use Avalon-ST Source and Sink BFMs to verify an Avalon-ST component

• The test program controls the BFMs using the BFM API to drive and monitor transactions.Figure 16-1: Top-Level Testbench for Avalon-ST DUT ComponentQ

3. The parallel processes terminate when the Avalon-ST Source and Sink BFM transaction queues are emptyand all four transactions are complete.4. The t

Table 16-2: Avalon-ST Single Clock FIFO Exported Interface NamesExport NameDescriptionInterface NameclkClock InputclkresetReset Inputclk_resetst_inAva

DescriptionHierarchy Variables Coding ExampleSets the Qsys simulation path to thedirectory that includes the ModelSimscript. You must set this path wh

Observing the ResultsYou can view the simulation results in the following two ways:• In the ModelSim transcript console• In the waveforms windowThe tr

Interrupt Source and Sink APIclear_irq()int clear_irq()Prototype:Verilog HDL: interrupt_bitVHDL: interrupt_bit, bfm_id, req_if(bfm_id)Arguments:voidRe

Figure 16-2: Timing from ModelSim SimulationThis figure shows the simulation timing from the ModelSim wave window.clkreset_bfm.resetclk_bfm_clk_clkres

17Avalon-MM Verilog HDL and VHDL TestbenchesSubscribeSend FeedbackAltera provides the Avalon-MM example testbench for both Verilog HDL and VHDL.There

The Slave Thread performs the following functions:• Randomly sets backpressure cycles to Avalon-MM Slave BFM• Waits for valid commands• Retrieves vali

The Qsys Generate window displays informational messages as it generates the testbench.d. Close the Generate window.4. Start the ModelSim®simulator.5.

Running the Verilog HDL Testbench for the Two Avalon-MM Masters and Slaves1. Unzip ug_avalon_verification.zip to a working directory.2. Open <worki

Figure 17-3: Avalon-MM Master0 and Slave0 Writestb.clktb.resetm0_waitrequestm0_writem0_readm0_readdatavalidm0_address[12:0]m0_burstcount[3:0]m0_writed

Figure 17-4: Avalon-MM Master0 and Slave0 Reads..0F0C'b .116C4 3F FC.0.7.9.000000003.2FD 2FE 2FF 300 301 302 3C33C45 4 3 2 1 4 3.3. .2635FB4C.4.4

The Master Command Thread performs the following functions:• Generates random commands• Passes the commands to Avalon-MM Master BFM• Saves the command

The Qsys Generate window displays informational messages as it generates the testbench.d. Close the Generate window.4. Start the ModelSim®simulator.5.

Running the Testbench for Two Avalon-MM Masters Slaves1. Unzip ug_avalon_verification.zip to a working directory.2. Open <working_dir>/avlm_avls

set_irq()set_irq()set_irq()Prototype:Verilog HDL: int interrupt_bitVHDL: int interrupt_bit, bfm_id, req_if(bfm_id)Arguments:voidReturns:Asserts the in

Figure 17-8: Timing for a Write Burst with a Burst Count of Fourtb.clktb.resetmstr1_m0_waitrequestmstr1_m0_writemstr1_m0_readmstr1_m0_readdatavalidmst

master BFM, include the package for this BFM in your test program. Packages are named: <BFM type orcomponent name>_vhdl_pkgThe VHDL BFM design a

18Document Revision HistorySubscribeSend FeedbackThe following table shows the revision history for this document.ChangesVersionDateMade the following

ChangesVersionDate• Updated SOPC Tutorial chapter.• Updated Qsys Tutorial chapter.3.1June 2012How to Contact AlteraAddressContact MethodContact (1)www

MeaningVisual CueIndicates signal, port, register, bit, block, and primitive names. Forexample, data1, tdi, and input. The suffix n denotes an active-

5Avalon-MM Master BFMSubscribeSend FeedbackThe Avalon-MM Master BFM implements the Avalon-MM interface protocol, including: read, write, burstread, an

TimingThe following timing diagram illustrates the sequence of events for an Avalon-MM Master BFM. The MasterBFM drives interleaved writes and reads w

Table 5-1: Key to the AnnotationsThe following table lists the annotations used in the figure.DescriptionSymbolThe initial command latency, which is t

Figure 5-3: Avalon-MM Master Driving Write and Read Transactions with No readdatavalid SignalThe timing in the following figure shows the sequence of

DescriptionSymbolSignals when write and read commands are presented on the interface. The event name issignal_command_issued.Sci_1–Sci_2Signals the fi

• Public Events—Provides status response that arrives together with the data. The public event signalsindicate the status of the Master’s request, suc

Table 5-3: Parameters for the Avalon-MM Master BFMDescriptionLegal ValuesDefaultValueParameterPort WidthsAddress width in bits.N/A32Address widthData

event_command_issued()...5-10event_max_comma

DescriptionLegal ValuesDefaultValueParameterWhen On, the interface includes a writeresponse pin.On/OffOffUse the write responsesignalsWhen On, the int

DescriptionLegal ValuesDefaultValueParameterSpecifies whether to turn on the register stage.On/OffOffRegistered waitrequestSpecifies whether to regist

event_command_issued()event_command_issued()Prototype:Verilog HDL: N.A.VHDL: bfm_idArguments:voidReturns:Notifies the testbench a command was driven t

event_response_complete()event_response_complete()Prototype:Verilog HDL: N.A.VHDL: bfm_idArguments:voidReturns:Notifies the testbench that a read/writ

get_command_pending_queue_size()int get_command_pending_queue_size()Prototype:Verilog HDL: NoneVHDL: command_pending_queue_size, bfm_id, req_if(bfm_id

get_response_byte_enable()bit [AV_NUMSYMBOLS-1:0] get_response_byte_enable(int index)Prototype:Verilog HDL: indexVHDL: response_byte_enable, index, bf

get_response_latency()int get_response_latency(int index)Prototype:Verilog HDL: indexVHDL: response_data, index, bfm_id, req_if(bfm_id)Arguments:bitRe

get_response_read_response()bit[2**(AV_BURSTCOUNT_W-1) - 1:0] [AV_READRESPONSE_W-1:0] get_response_read_response(int index)Prototype:Verilog HDL: int

get_response_write_id()bit [AV_TRANSACTIONID_W-1:0] get_response_write_id()Prototype:Verilog HDL: NoneVHDL: response_write_id, index, bfm_id, req_if(b

get_version()string get_version()Prototype:Verilog HDL: NoneVHDL: N.A.Arguments:StringReturns:Returns BFM version as a string of three integers separa

set_command_transaction_id() ...5-22set_command_write_r

push_command()void push_command()Prototype:Verilog HDL: NoneVHDL: bfm_id, req_if(bfm_id)Arguments:voidReturns:Inserts the fully populated transaction

set_command_arbiterlock()void set_command_arbiterlock (bit state)Prototype:Verilog HDL: bit stateVHDL: bit state, bfm_id, req_if(bfm_id)Arguments:void

set_command_burst_size()void set_command_burst_size (bit[AV_BURSTCOUNT_W-1:0] burst_size)Prototype:Verilog HDL: burst_sizeVHDL: burst_size, bfm_id, re

set_command_idle()void set_command_idle(int idle, int index)Prototype:Verilog HDL: int idle, int indexVHDL: int idle, int index, bfm_id, req_if(bfm_id

set_command_request()void set_command_request(Request_t request)Prototype:Verilog HDL: Request_t requestVHDL: Request_t request, bfm_id, req_if(bfm_id

set_command_write_response_request()void set_command_write_response_request (logic request)Prototype:Verilog HDL: requestVHDL: request, bfm_id, req_if

set_response_timeout()void set_response_timeout(int cycles)Prototype:Verilog HDL: int cyclesVHDL: int cycles, bfm_id, req_if(bfm_id)Arguments:voidRetu

signal_fatal_errorsignal_fatal_errorPrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Notifies the testbench that a fatal error has occured i

signal_read_response_completesignal_read_response_completePrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Signals that the read response ha

6Avalon-MM Slave BFMSubscribeSend FeedbackThe Avalon-MM Slave BFM implements the slave side of the Avalon-MM interface protocol. The Avalon-MMprotocol

get_response_queue_size() ...6-16vget_slave_bfm

The BFMs allow illegal response transactions so that you can test the error-handling functionalityof your DUT. Consequently, the BFMs cannot be relied

Figure 6-2: Avalon-MM Slave Responding to Interleaved Write and Read TransactionsCLKreadtransaction1 transaction2trans3trans4writeScr_1waitrequestbyte

Table 6-1: Key to AnnotationsThe following table lists the annotations used in this figure.DescriptionSymbolThe response wait time, which is three cyc

Figure 6-3: Avalon-MM Slave Receiving Write and Read Commands with No readdatavalid SignalThe following timing diagram illustrates the sequence of eve

DescriptionSymbolSignals the end of the test. The event name is signal_all_transactions_completeSatcBlock DiagramThe following figure provides a block

• Public Events—Provides status response that arrives together with the data. The public event signalsindicate the status of the Master’s request such

DescriptionLegalValuesDefaultValueParameterData symbol width in bits. Set AV_SYMBOL_W to 8 forbyte-oriented interfaces.N/A8Symbol widthRead status res

DescriptionLegalValuesDefaultValueParameterWhen On, read is asserted high.On/OffOnAssert read highWhen On, write is asserted high.On/OffOnAssert write

Avalon-MM Slave BFM APIevent_error_exceed_max_pending_reads()event_error_exceed_max_pending_reads()Prototype:Verilog HDL: N.A.VHDL: bfm_id, req_ifArgu

event_max_response_queue_size()event_max_response_queue_size()Prototype:Verilog HDL: N.A.VHDL: bfm_idArguments:voidReturns:Notifies the testbench that

set_enable_a_constant_during_burst() ...7-7set_enable_a_constant_d

get_command_arbiterlock()bit get_command_arbiterlock()Prototype:Verilog HDL: NoneVHDL: command_arbiterlock, bfm_id, req_if(bfm_id)Arguments:bitReturns

get_command_byte_enable()bit [AV_NUMSYMBOLS-1:0] get_command_byte_enable (int index)Prototype:Verilog HDL: indexVHDL: command_byte_enable, index, bfm_

get_command_queue_size()int get_command_queue_size()Prototype:Verilog HDL: NoneVHDL: command_queue_size, bfm_id, req_if(bfm_id)Arguments:intReturns:Qu

get_command_transaction_id()AvalonTransactionId_t get_command_transaction_id()Prototype:Verilog HDL: NoneVHDL: command_transaction, bfm_id, req_if(bfm

get_pending_write_latency_cycle()int get__cycle()Prototype:Verilog HDL: NoneVHDL: pending_write_latency, bfm_id, req_if(bfm_id)Arguments:intReturns:Qu

get_version()string get_version()Prototype:Verilog HDL: NoneVHDL: N.A.Arguments:StringReturns:Returns BFM version as a string of three integers separa

push_response()void push_response()Prototype:Verilog HDL: NoneVHDL: bfm_id, req_if(bfm_id)Arguments:voidReturns:Inserts the fully populated response t

vset_max_response_queue_size()void set_max_response_queue_size(int size)Prototype:Verilog HDL: int sizeVHDL: int size, bfm_id, req_if(bfm_id)Arguments

set_response_burst_size()void set_response_burst_size(bit [AV_BURSTCOUNT_W-1:0] burst_size).Prototype:Verilog HDL: burst_sizeVHDL: burst_size, bfm_id,

set_response_request()void set_response_request(Request_t request)Prototype:Verilog HDL: Request_t requestVHDL: Request_t request, bfm_id, req_if(bfm_

init() ...

set_write_response_status()void set_write_respose_status(AvalonWriteResponse_t status, intindex)Prototype:Verilog HDL: AvalonWriteResponse_t status, i

signal_max_response_queue_sizesignal_max_response_queue_sizePrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Signals that the maximum pendin

signal_response_issuedsignal_response_issuedPrototype:Verilog HDL: NoneVHDL: N.A.Arguments:voidReturns:Notifies the testbench that a response has been

7Avalon-MM MonitorSubscribeSend FeedbackThe Avalon-MM Monitor verifies Avalon-MM interfaces using SystemVerilog assertions. In addition, itprovides te

ParametersThe Avalon-MM Monitor supports the full range of signals defined for the Avalon-MM master and slaveinterfaces. You can customize the Avalon-

DescriptionLegalValuesDefaultValueParameterWhen On, the interface includes a writeresponsepin.On/OffOffUse the writeresponse signalWhen On, the interf

DescriptionLegalValuesDefaultValueParameterFor master interfaces that do not use the waitrequestsignal. The read wait time indicates the number ofcycl

set_enable_a_beginbursttransfer_exist()set_enable_a_beginbursttransfer_exist()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables an

set_enable_a_begintransfer_exist()set_enable_a_begintransfer_exist()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables an assertion

set_enable_a_burst_legal()set_enable_a_burst_legal()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables an assertion that ensures th

init() ...

set_enable_a_constant_during_clk_disabled()set_enable_a_constant_during_clk_disabled()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:En

set_enable_a_half_cycle_reset_legal()set_enable_a_half_cycle_reset_legal()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables an ass

set_enable_a_no_readdatavalid_during_reset()set_enable_a_no_readdatavalid_during_reset()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:

set_enable_a_readid_sequence()set_enable_a_readid_sequence()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables an assertion that ve

set_enable_a_register_incoming_signals()set_enable_a_register_incoming_signals()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables

set_enable_a_write_burst_timeout()set_enable_a_write_burst_timeout()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables an assertion

set_enable_c_b2b_read_read()set_enable_c_b2b_read_read()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables a coverage group to test

set_enable_c_b2b_write_write()set_enable_c_b2b_write_write()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables a coverage group to

set_enable_c_continuous_waitrequest()set_enable_c_continuous_waitrequest()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables a cove

set_enable_c_continuous_write()set_enable_c_continuous_write()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables a coverage group t

get_input_transaction_queue_size()...12-4get_output_transactio

set_enable_c_idle_in_read_response()set_enable_c_idle_in_read_response()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables a covera

set_enable_c_read()set_enable_c_read()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables a coverage group to test read transfers. T

set_enable_c_read_byteenable()set_enable_c_read_byteenable()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables a coverage group ens

set_enable_c_waitrequest_in_write_burst()set_enable_c_waitrequest_in_write_burst()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enable

set_enable_c_waitrequested_write()set_enable_c_waitrequested_write()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables a coverage g

set_enable_c_write_after_reset()set_enable_c_write_after_reset()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables a coverage group

set_enable_c_write_response()set_enable_c_write_response()Prototype:Verilog HDL: BooleanVHDL: N.A.Arguments:voidReturns:Enables a coverage group to te

event_command_received()event_command_received()Prototype:Verilog HDL: N.A.VHDL: bfm_idArguments:voidReturns:Notifies the testbench that a command was

get_clken()logic get_clken()Prototype:Verilog HDL: NoneVHDL: clken, bfm_id, req_if(bfm_id)Arguments:logicReturns:Returns the clock enable signal statu

get_command_burst_count()[AV_BURSTCOUNT_W-1:0] get_command_burst_count()Prototype:Verilog HDL: NoneVHDL: command_burst_count, bfm_id, req_if(bfm_id)Ar