Altera Avalon Verification IP Suite Manuale Utente Scaricare il pdf (Pagina 217)

The Master Command Thread performs the following functions:

• Generates random commands

• Passes the commands to Avalon-MM Master BFM

• Saves the commands in a FIFO for command and response verification

• For read commands, the master waits for a valid response and verifies it against the expected read data.

The Slave Thread performs the following functions:

• Randomly sets backpressure cycles to Avalon-MM Slave BFM

• Waits for valid commands

• Retrieves valid commands from the Avalon-MM Slave BFM

• Verifies commands against the expected command

• Sends read data for read commands. The read data is saved in a FIFO for verification

The test program sends the following transaction types:

• Non-bursting writes

• Non-bursting reads

• Bursting writes

• Bursting reads

Running the Testbench for a Single Avalon-MM Master and Slave Pair

1. Unzip ug_avalon_verification.zip to a working directory.

2. Open <working_dir>/avlm_avls_1x1.qsys.

3. Complete the following steps to generate the testbench:

a. On the Generate menu, select Generate HDL.

b. Specify the parameters shown in the following table:

Table 17-3: Generation Parameters

ValueParameter

Synthesis

Leave this option offCreate HDL design files for synthesis

Leave this option offCreate timing and resource estimates for third-party

EDA synthesis tools

Leave this option onCreate block symbol file (.bsf)

Simulation

VHDLCreate simulation model

Leave this option offAllow mixed-language simulation

Output Directory

<working_dir>/avlm_avls_1x1Path

c. Click Generate.

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Avalon-MM Verilog HDL and VHDL Testbenches

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Running the Testbench for a Single Avalon-MM Master and Slave Pair

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Altera Avalon Verification IP Suite Manuale Utente Pagina 217