
set_enable_a_beginbursttransfer_exist()
set_enable_a_beginbursttransfer_exist()Prototype:
Verilog HDL: Boolean
VHDL: N.A.
Arguments:
voidReturns:
Enables an assertion that ensures beginbursttransfer is asserted during
a transfer. It is disabled when beginbursttransfer is not used.
Description:
Verilog HDLLanguage support:
set_enable_a_beginbursttransfer_legal()
set_enable_a_beginbursttransfer_legal()Prototype:
Verilog HDL: Boolean
VHDL: N.A.
Arguments:
voidReturns:
Enables an assertion that ensures beginbursttransfer is asserted with a
read or write signal. It is disabled when beginbursttransfer is not used.
Description:
Verilog HDLLanguage support:
set_enable_a_beginbursttransfer_single_cycle()
set_enable_a_beginbursttransfer_single_cycle()Prototype:
Verilog HDL: Boolean
VHDL: N.A.
Arguments:
voidReturns:
Enables an assertion that ensures beginbursttransfer is asserted for a
single cycle regardless of the behavior of the waitrequest signal. It is disabled
when beginbursttransfer is not used.
Description:
Verilog HDLLanguage support:
Altera Corporation
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set_enable_a_beginbursttransfer_exist()
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