
DescriptionLegal ValuesDefault
Value
Parameter
Specifies whether to turn on the register stage.On/OffOffRegistered waitrequest
Specifies whether to register incoming signals.On/OffOffRegistered Incoming
Signals
Interface Address Type
Sets slave interface address type to symbols or words.WORDS/
SYMBOLS
WORDSSet master interface
address type to symbols
or words
Avalon-MM Master BFM API
all_transactions_complete()
bit all_()Prototype:
Verilog HDL: None
VHDL:transactions_complete_status, bfm_id, req_if(bfm_id)
Arguments:
bit.Returns:
Queries the BFM component to determine whether all issued commands have
been completed. A return value of 1 means that there are no more transactions
in the transaction queue or in progress.
Description:
Verilog HDL, VHDLLanguage support:
event_all_transactions_complete()
event_all_transactions_complete()Prototype:
Verilog HDL: N.A.
VHDL: bfm_id
Arguments:
voidReturns:
Notifies the testbench that all commands have completed.Description:
VHDLLanguage support:
Altera Corporation
Avalon-MM Master BFM
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Avalon-MM Master BFM API
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