Altera Serial Digital Interface (SDI) MegaCore Function Manuale Utente Pagina 85
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Chapter 3: Functional Description 3–55
Signals
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
PLL_SCANCLK
(7)
,
(8)
,
(9)
Input
Drives the
scanclk
signal on the transceiver PLL to be
reconfigured.
PLL_SCANCLKENA
(7)
,
(8)
,
(9)
Input
Acts as a clock enable for the
scanclk
signal on the transceiver
PLL to be reconfigured.
PLL_SCANDATA
(7)
,
(8)
,
(9)
Input
Drives the
scandata
signal on the transceiver PLL to be
reconfigured. This signal holds the scan data input to the
transceiver PLL for the dynamically reconfigurable bits.
PLL_SCANDONE
(7)
,
(8)
,
(9)
Output Determines when the transceiver PLL is reconfigured.
PLL_SCANDATAOUT
(7)
,
(8)
,
(9)
Output
This signal holds the transceiver PLL scan data output from the
dynamically reconfigurable bits.
Notes to Table 3–19:
(1) These signals must be connected directly to a reconfiguration megafunction.
(2) The transceivers are available for Arria GX, Arria II GX, Arria V, Cyclone IV GX, Cyclone V, Hardcopy IV GX, Stratix II GX, Stratix IV, and Stratix V
devices only.
(3) SDI transmitters do not require the use of transceiver dynamic reconfiguration but to enable the cores to merge into a transceiver quad that has
transceiver dynamic reconfiguration enabled, you must connect these ports correctly.
(4) In the Quartus II software version 8.1 and later, the Stratix IV transceivers requires receiver buffer calibration through an
ALTGX_RECONFIG
(transceiver dynamic reconfiguration) controller. The additional RECONFIG port bits are used for receiver buffer calibration. You must connect
these ports to the
ALTGX_RECONFIG
controller externally. For further information on the receiver buffer calibration, refer to the Stratix IV
Dynamic Reconfiguration chapter in volume 2 of the Stratix IV Device Handbook. If you are using the Quartus II software version 10.1, make
sure to upgrade the SDI MegaCore function to version 10.1 as well.
(5) N represents the number of channels instantiated.
(6) The
SDI_GXB_POWERDOWN
signal of all the instances that are to be combined in a single transceiver block must be connected to a single point
(same input or same logic). Any difference in the driving logic prevents the instances from being combined in a single transceiver block.
(7) This signal must be connected directly to the ALTPLL_RECONFIG megafunction, and only exposed to the top level when you select the Use PLL
reconfiguration for transceiver dynamic reconfiguration option in the SDI parameter editor.
(8) The transceivers are available for Cyclone IV GX devices only.
(9) You require
rx_std
and
sdi_start_reconfig
signals for PLL reconfiguration.
Table 3–19. Transceiver Dynamic Reconfiguration Signals (Part 2 of 2)
Signal Direction Description
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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