Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core Manuale Utente Scaricare il pdf

Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core

User Guide

2015.05.04

UG-01155

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The Altera IOPLL megafunction IP core allows you to configure the settings of Arria

10 I/O PLL.

Altera IOPLL IP core supports the following features:

• Supports six different clock feedback modes: direct, external feedback, normal, source synchronous,

zero delay buffer, and LVDS mode.

• Generates up to nine clock output signals for the Arria 10 device.

• Switches between two reference input clocks.

• Supports adjacent PLL (adjpllin) input to connect with an upstream PLL in PLL cascading mode.

• Generates the Memory Initialization File (.mif) and allows PLL dynamic reconfiguration.

• Supports PLL dynamic phase shift.

Related Information

• Introduction to Altera IP Cores

Provides more information about the Altera IP cores and the parameter editor.

• Operation Modes on page 8

• Output Clocks on page 8

• Reference Clock Switchover on page 9

• PLL-to-PLL Cascading on page 9

Device Family Support

The Altera IOPLL IP core only supports the Arria 10 device family.

Altera IOPLL IP Core Parameters

The Altera IOPLL IP core parameter editor appears in the PLL category of the IP Catalog.

Altera IOPLL IP Core Parameters - PLL Tab

Table 1: Altera IOPLL IP Core Parameters - PLL Tab

Parameter Legal Value Description

Device Family Arria 10 Specifies the device family.

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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

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Pagina 1 - User Guide

Altera I/O Phase-Locked Loop (Altera IOPLL) IP CoreUser Guide2015.05.04UG-01155SubscribeSend FeedbackThe Altera IOPLL megafunction IP core allows you

Pagina 2

Parameter Type Condition Descriptionfbclk Input OptionalThe external feedback input port for the I/OPLL.The Altera IOPLL IP core creates this port whe

Pagina 3

Document Revision HistoryDate Version ChangesMay 2015 2015.05.04 Updated the description for Enable access to PLL LVDS_CLK/LOADENoutput port parameter

Pagina 4

Parameter Legal Value DescriptionComponent — Specifies the targeted device.Speed Grade — Specifies the speed grade for targeted device.PLL Mode Intege

Pagina 5

Parameter Legal Value DescriptionNumber of Clocks 1–9 Specifies the number of output clocks required for eachdevice in the PLL design. The requested s

Pagina 6 - Related Information

Parameter Legal Value DescriptionMultiply Factor (M-Counter) (2)4–511Specifies the multiply factor of M-counter.The legal range of the M counter is 4–

Pagina 7 - Functional Description

Parameter Legal Value DescriptionSwitchover Mode AutomaticSwitchover,ManualSwitchover, orAutomaticSwitchoverwith ManualOverrideSpecifies the switchove

Pagina 8 - Output Clocks

Related InformationSignal Interface Between Altera IOPLL and Altera LVDS SERDES IP CoresProvides more information about PLL lvds_clk and loaden signal

Pagina 9 - PLL-to-PLL Cascading

Altera IOPLL IP Core Parameters - Advanced Parameters TabTable 5: Altera IOPLL IP Core Parameters - Advanced Parameters TabParameter Legal Value Descr

Pagina 10 - 2015.05.04

The following terms are commonly used to describe the behavior of a PLL:• PLL lock time—also known as the PLL acquisition time. PLL lock time is the t

Pagina 11 - Document Revision History

Each output clock has a set of requested settings where you can specify the desired values for outputfrequency, phase shift, and duty cycle. The desir

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