Altera Advanced SEU Detection IP Core Manuale Utente

Altera Advanced SEU Detection IP Core User Guide2015.05.04ALTADVSEUSubscribeSend FeedbackThe Altera Advanced SEU Detection IP core contains the follow

Revision 2 SMHFigure 7: Revision 2 SMH32 bit ID: 0xXX445341frame_info Base Addressoffset_map Base Addresssensitivity_data_array Base Addresssingle_off

• Frame information array—contains a 32-bit string for each frame in the device. The frame numberserves as the index for the frame information string.

Figure 8: IP Core Installation Pathacdsquartus - Contains the Quartus II softwareip - Contains the Altera IP Library and third-party IP coresaltera -

Figure 9: Quartus II IP CatalogSearch for installed IP coresDouble-click to customize, right-click for detailed informationShow IP only for target dev

Figure 10: IP Parameter EditorsView IP portand parameter detailsApply preset parameters forspecific applicationsSpecify your IP variationname and targ

Files Generated for Altera IP CoresThe Quartus II software generates the following IP core output file structure:Figure 11: IP Core Generated Files<

File Name Description<system>.sopcinfo Describes the connections and IP component parameterizations inyour Qsys system. You can parse its conten

File Name Description<my_ip>.regmap If the IP contains register information, the .regmap file generates.The .regmap file describes the register

Altera Advanced SEU Detection IP Core ParametersParameterGroupParameterDescriptionName Legal ValueGeneralCRC error cache depth 2, 4, 8,16, 32,64• Spec

The .smh contains a mask for design sensitive bits in a compressed format. The sensitivity mask isgenerated for the entire design. Hierarchy tagging p

Altera Advanced SEU Detection IP core interprets the error detection register of the error detection block,and then compares single-bit error location

Programming a Sensitivity Map Header File into a MemoryYou can program a .smh into any type of memory. For example, to use CFI flash memory, follow th

• Offset array for current frame = offset_map_array_index * offset_map_length• Offset data value for current byte and bit = [(byte * 8) + bit] * 2• Re

Note: The possible values for sensitivity_data_tag_size field are 1,2,4 or 8 that allows to supporta maximal of 255 possible non-zero region masks for

On-Chip Processing SignalsFigure 2: Altera Advanced SEU Detection Core Signals for On-Chip Processingclkresetcache_comparison_offdatavaliderroraddress

Interface Signals Type Width DescriptionErrors Outputnoncritical_error Output1 Indicates that an SMH lookup determined thatthe EDCRC error is in a non

Off-Chip Lookup Sensitivity ProcessingThe Altera Advanced SEU Detection IP core interprets the content of the error detection block’s EMRand presents

Off-Chip Lookup Sensitivity Processing Operation FlowFigure 4: Off-Chip Lookup Sensitivity Processing Operation FlowCRC Error Writes a Value into EMRC

Figure 5: Altera Advanced SEU Detection Core Signals for Off-Chip Processingclkresetcache_comparison_offdatavaliderrordatavalidreadyerrorcache_fill_le

Interface Signals Type Width DescriptionExternalMemoryAvalon-MMMastercache_data Output34• Error cache data.• This is the location information for an E

Revision 1 SMHFigure 6: Revision 1 SMHSensitivity Data ArrayOffset MapsFrame Information Array single_offset_map_lengthsensitivity_data_array Base Ad