Altera Active Serial Memory Interface Manuale Utente

Altera ASMI Parallel IP Core User Guide2014.12.15UG-ALT1005SubscribeSend FeedbackAbout This IP CoreThe Altera ASMI Parallel IP core provides access to

Parameter Legal Values DescriptionsUse ‘read_address’ port —• This signal holds the address from which data is beingread. This signal works together w

Parameter Legal Values DescriptionsDisable dedicated ActiveSerial interface—• This option is disabled by default and the IP coregenerates the design f

• on page 31For more information about the Use ‘bulk_erase’ port parameter• on page 30For more information the Use 'sector_erase' port param

Port Condition Size Descriptionsex4b_addr Optional 1 bit To exit the 4-byte addressing mode when you use anEPCQ256/EPCQ-L256 or larger devices, pull t

Port Condition Size Descriptionsread_sid Optional 1 bit Active-high port that executes the read silicon ID operation.If asserted, the IP core proceeds

Port Condition Size Descriptionswren Optional 1 bit Active-high port that allows write and erase operations to beperformed as long as it stays asserte

• on page 21For more information about the sector protect operation• on page 26For more information about the write operation• on page 26For more info

Port Condition Size Descriptionsepcs_id[] Optional 8 bit Contains the silicon ID of the EPCS device after the readsilicon ID operation. This port hold

• on page 18For more information about the erase operation• on page 26For more information about the write operation• on page 19For more information a

• Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L Device• Read Silicon ID from the EPCS Device• Protect a Sector on the EPCS/EPCQ/EPCQ-L Device• Rea

This figure shows that you can use the Altera ASMI Parallel IP core to access the general purpose memoryportion of the EPCS/EPCQ/EPCQ-L devices throug

The rdid_out[7..0] signal holds the value of the memory capacity ID until the device resets.Therefore, you must execute this read command only once.No

Protect a Sector on the EPCS/EPCQ/EPCQ-L DeviceUse the sector_protect signal to instruct the IP core to protect a sector on the EPCS/EPCQ/EPCQ-Ldevice

Related Information• Serial Configuration Devices DatasheetFor more information about the block protection level for EPCQ devices. Every devices have

The first data byte then appears on the dataout[7..0] signal. The IP core then asserts thedata_valid signal for one clock cycle, which indicates that

Figure 8: Fast Reading Multiple-ByteThis figure shows an example of the latency when the Altera ASMI Parallel IP core is executing multiple-byte fast

operation. Therefore, the fast read operation performs faster than the read operation. The IP coreasserts the data_valid signal for one clock cycle, t

when selecting EPCQ/EPCQ-L quad I/O fast read operation, the IP core generates the first byte of data onthe dataout[7..0] port after ten cycles, and t

Single-Byte Write OperationThis figure shows an example of the latency when the Altera ASMI Parallel IP core is performing a single-byte write operati

Figure 12: Page-Write Operation: Example 1This figure shows an example of the page-write operation when the PAGE_SIZE parameter has a value ofeight.Fi

EPCQ/EPCQ-L device, and discards the first few bytes. This behavior is consistentwith the EPCS/EPCQ/EPCQ-L device itself.Note: The shift_bytes, wren,

Ports and ParametersThis figure shows a typical block diagram of the Altera ASMI Parallel IP core.Figure 1: Altera ASMI Parallel Block DiagramAltera A

Figure 14: Reading a Status RegisterThis figure shows an example of the latency when the Altera ASMI Parallel IP core is executing the readstatus regi

Figure 15: Erasing Memory in a Specified SectorThis figure shows an example of the latency when the Altera ASMI Parallel IP core is executing the eras

Figure 16: Erasing Memory in BulkThis figure shows an example of the latency when the Altera ASMI Parallel IP core is executing the erasememory in bul

Figure 17: Erasing Memory in a Specified DieThis figure shows an example of the latency when the Altera ASMI Parallel IP core is executing the eraseme

Figure 18: Execution of 4BYTEADDREN For Enabling 4-byte Addressing ModeThis figure shows an example of the latency when the Altera ASMI Parallel IP co

Date Version ChangesMay 2013 4.1• Replaced the term dummy bytes with dummy cycles.• Removed the Use ‘die_erase’ port parameter in Table 2–1 on page 2–

Date Version ChangesOctober 2007 2.4• Updated for new MegaWizard™ Plug-In Manager pages• Updated to include information about new fast_read commandMay

ParametersTable 1: Parameter SettingsParameter Legal Values DescriptionsCurrently selected devicefamilyArria GX,Arria V GZ,Arria II GX,Arria II GZ,Arr

Parameter Legal Values DescriptionsConfiguration devicetypeEPCS1,EPCS4,EPCS16,EPCS64,EPCS128,EPCQ16,EPCQ32,EPCQ64,EPCQ128,EPCQ256,EPCQ512,EPCQ-L256,EP

Parameter Legal Values DescriptionsUse ‘read_rdid’ and‘rdid_out’ ports—• Enables the ability to read the memory capacity ID ofthe EPCS/EPCQ/EPCQ-L dev

Parameter Legal Values DescriptionsWrite mode —• This option is only available when you turn on theEnable ‘write’ operation option.• When you select t

Parameter Legal Values DescriptionsChoose I/O mode STANDARD,DUAL, QUAD• The following commands are the instructions from theEPCQ/EPCQ-L extended seria

Parameter Legal Values DescriptionsUse ‘sector_protect’ port —• Enables the ability to protect sectors in the EPCS/EPCQ/EPCQ-L device from write and e