Altera Triple Speed Ethernet MegaCore Function Manuale Utente

Triple-Speed Ethernet MegaCore FunctionUser GuideLast updated for Altera Complete Design Suite: 14.0101 Innovation DriveSan Jose, CA 95134www.altera.c

Small MAC10/100/1000 Ethernet MACFeatureLimited programmable options. The following optionsare fixed:• Maximum frame length is fixed to 1518. Jumbofra

HW ResetDescriptionR/WNameDwordOffset0x0Static timing adjustment in fractionalnanoseconds for outbound timestamps on thereceive datapath.• Bits 0 to 1

Table 6-10: IEEE 1588v2 Feature PMA Delay—Simulation ModelTiming AdjustmentDeviceDelayRX registerTX register33.5 UI11 UIStratix V or Arria V GZDigital

• For PCS registers, map the registers to the dword offsets in the MAC register space before you convertthe dword offsets to byte offsets:• if_mode wo

DescriptionR/WRegister NameWordOffsetThe PCS function revision. Always set to the current versionof the MegaCore function.ROrev0x1121-bit auto-negotia

DescriptionR/WNameBit(s)Enables the unidirectional function. This bit depends on bit12. When bit 12 is one, this bit is ignored.When bit 12 is zero, b

DescriptionR/WNameBit(s)Self-clearing reset bit. Set this bit to 1 to generate asynchronous reset pulse which resets all the PCS functionstate machine

DescriptionR/WNameBitThe PCS function does not support 100Base-T2,10-Mbps, 100BASE-X, and 100Base-T4 operation.Always set to 0.RO100BASET2_HALF_DUPLEX

DescriptionR/WNameBit(s)Remote fault condition:• RF1=0 / RF2=0: No error, link is valid (resetcondition).• RF1=0 / RF2=1: Offline.• RF1=1 / RF2=0: Fai

DescriptionR/WNameBit(s)Acknowledge. A value of 1 indicates that the linkpartner has received 3 consecutive matching abilityvalues from the device.ROA

An_Expansion Register (Word Offset 0x06)Table 6-18: An_Expansion Register DescriptionDescriptionR/WNameBit(s)A value of 1 indicates that the link part

Figure 1-2: Multi-port MAC10/100/1000-MbpsEthernet MACMII/GMII/RGMIIClient SideNetwork SideAvalon-ST(Transmit and Receive)Avalon-MM(Management and Con

DescriptionR/WNameBit(s)SGMII half-duplex mode. Setting this bit to 1 enableshalf duplex for 10/100 Mbps speed. This bit is ignoredwhen SGMII_ENA is 0

Triple-Speed Ethernet System with MII/GMII or RGMIIFigure 6-2: Triple-Speed Ethernet System with MII/GMII or RGMII with Register Initialization Recomm

Tx_section_full = 16//Cut Throught Mode, Set this Threshold to 0 to enable Store and Forward ModeRx_section_full = 16c. MAC Address Configuration//MAC

Triple-Speed Ethernet System with SGMIIFigure 6-3: Triple-Speed Ethernet System with SGMII with Register Initialization Recommendation10/100/1000 Mbps

PCS Control Register = 0x9140Wait PCS Control Register RESET bit is clear3. MAC Configuration Register InitializationRefer to step 2 in Triple-Speed E

//AUTO_NEGOTIATION_ENA = 1, Bit 6,8,13 is Read OnlyPCS Control Register = 0x1140d. PCS Reset//PCS Software reset is recommended where there any config

7Interface Signals2014.06.30UG-01008SubscribeSend FeedbackInterface SignalsThe following sections describe the Triple-Speed Ethernet MegaCore function

10/100/1000 Ethernet MAC SignalsFigure 7-1: 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers Signals10/100/1000 Ethernet MACPHYManagementS

DescriptionI/ONameGMII /RGMII/ MII receive clock. Provides the timing reference forall rx related signals. The values of gm_rx_d[7:0], gm_rx_dv, gm_rx

DescriptionI/ONameGigabit mode selection. Can be driven to 1 by an external device, forexample a PHY device, to set the MAC function to operate in gig

Figure 1-5: Stand-Alone 10/100/1000 Mbps Ethernet MACGigabit or FastEthernet PHYDeviceUserApplicationHost Interface MDIO M asterAltera DeviceTriple-Sp

DescriptionI/OAvalon-ST SignalTypeNameReceive start of packet. Asserted when the firstbyte or word of a frame is driven on ff_rx_data[(DATAWIDTH-1):0]

DescriptionBitIndicates broadcast frames. Asserted with ff_rx_sop and remains asserted until the end ofthe frame.2Indicates multicast frames. Asserted

DescriptionI/OAvalon-ST SignalTypeNameTransmit data write enable. Assert this signal toindicate that the data on the following signals arevalid: ff_tx

DescriptionI/OAvalon-ST SignalTypeNameAsserted when an underflow occurs on thetransmit FIFO buffer.O—tx_ff_uflowDeasserted when the FIFO buffer is fil

DescriptionI/ONameAssert this active-low signal to put the node into a power-down state.If magic packets are supported (the MAGIC_ENA bit in the comma

DescriptionI/ONameRGMII control input signal. Expects gm_rx_dv on the positive edge ofrx_clk and a logical derivative of (gm_rx_dv XOR gm_rx_err) on t

ECC Status SignalsTable 7-12: ECC Status SignalsDescriptionI/ONameECC status indication.• 11: An uncorrectable error occurred and the error data appea

10/100/1000 Multiport Ethernet MAC SignalsFigure 7-2: 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers SignalsMulti -Port MAC

DescriptionI/OAvalon-ST SignalTypeNameTransmit MAC clock (2.5/25/125 MHz) for theAvalon-ST transmit data interface.Oclkmac_tx_clkMultiport MAC Receive

DescriptionI/OAvalon-ST SignalTypeNameTransmit data valid. Assert this signal to indicatethat the data on the following signals are valid:data_tx_data

directly to a gigabit interface converter (GBIC), small form-factor pluggable (SFP) module, or an SGMIIPHY.Figure 1-7: 10/100/1000 Mbps Ethernet MAC a

DescriptionI/OAvalon-ST SignalTypeNameClassification presented at the beginning of eachpacket:Bit 4—Set to 1 for unicast frames.Bit 3—Set to 1 for bro

SectionInterface SignalPause and Magic Packet Signals on page 7-8Pause and magic packet signalsMII/GMII/RGMII Signals on page 7-9MII/GMII/RGMII interf

DescriptionI/OName125-MHz TBI transmit clock from external SERDES, typically sourcedby the local reference clock oscillator.Itbi_tx_clk125-MHz TBI rec

Arria 10 Transceiver Native PHY SignalsTable 7-22: Arria 10 Transceiver Native PHY SignalsDescriptionI/ONameSerial clock input from the transceiver PL

ECC Status SignalsTable 7-23: ECC Status SignalsDescriptionI/ONameECC status indication.11: An uncorrectable error occurred and the error data appears

10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS SignalsFigure 7-4: 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buff

SectionInterface SignalMultiport MAC FIFO Status Signals on page 7-15MAC FIFO status signalsPause and Magic Packet Signals on page 7-8Pause and magic

10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA SignalsFigure 7-5: 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers, a

reconfig_clk, and reconfig_busy—are not present in variations targeting Stratix V devices with GXtransceivers.1.25 Gbps Serial InterfaceIf the variant

DescriptionI/ONameReference clock for the dynamic reconfiguration controller. If youuse a dynamic reconfiguration controller in your design todynamica

• MDIO access• Frame transmission and error handling• Frame reception and error handling• Ethernet frame MAC address filtering• Flow control• Retransm

10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMAFigure 7-6: 10/100/1000 Multiport Ethernet MAC Function without Internal

Table 7-28: ReferencesSectionInterface SignalClock and Reset Signal on page 7-2Clock and reset signalsMAC Control Interface Signals on page 7-3MAC con

DescriptionWidthI/OSignalWhen asserted, this signal indicates thatrx_ingress_timestamp_96b_datacontains valid timestamp.For all receive frame, the MAC

DescriptionWidthI/OSignalA transmit interface signal. Assert thissignal to indicate that a timestamp isobtained and a timestamp request is validfor th

IEEE 1588v2 TX Timestamp Request SignalsTable 7-31: IEEE 1588v2 TX Timestamp Request SignalsDescriptionWidthI/OSignalAssert this signal when a user-de

DescriptionWidthI/OSignalTimestamp format of the frame, which thetimestamp inserts.0: 1588v2 format (48-bits second field + 32-bits nanosecond field +

DescriptionWidthI/OSignalFormat of timestamp to be used forresidence time calculation.0: 96-bits (96-bits egress timestamp - 96-bits ingress timestamp

DescriptionWidthI/OSignalThe location of the checksum field, relativeto the first byte of the packet.Assert this signal in the same clock cycle asthe

IEEE 1588v2 PCS Phase Measurement Clock SignalTable 7-34: IEEE 1588v2 PCS Phase Measurement Clock SignalDescriptionWidthI/OSignalSampling clock to mea

1000BASE-X/SGMII PCS SignalsFigure 7-7: 1000BASE-X/SGMII PCS Function SignalsResetSignalsreset _rx_clkreset _tx_clkreset _reg _clkset _10set _100set _

Table 1-2: Arria II GX Performance and Resource UtilizationThe estimated resource utilization and performance of the Triple-Speed Ethernet MegaCore fu

PCS Control Interface SignalsTable 7-36: Register Interface SignalsDescriptionI/OAvalon-MM SignalTypeNameRegister access reference clock. Set the sign

Figure 7-8: Clock Enabler Signal Behavior125 MHz Clock25 MHz Clock EnableInput DataOutput Data0xAA0xAA0xBB0xBB0xCC0xCC0xDD0xDD0xEEGMIITable 7-39: GMII

DescriptionI/ONameAsserted by the PHY to indicate that the current frame contains errors.Omii_rx_errCollision detection. Asserted by the PCS function

Table 7-42: ReferencesSectionInterface SignalTBI Interface Signals on page 7-16Ten-bit interfaceStatus LED Control Signals on page 7-17Status LED sign

Table 7-43: ReferencesSectionInterface SignalPCS Reset Signals on page 7-35Reset signalsMII/GMII Clocks and Clock Enablers on page 7-35MII/GMII clocks

Figure 7-11: Receive Operation—MAC Without Internal FIFO Buffersmac_rx_clk_0data_rx_data_0[7:0]data_rx_sop_0data_rx_eop_0data_rx_ready_0data_rx_error_

Avalon-ST Transmit InterfaceFigure 7-14: Transmit Operation—MAC With Internal FIFO Buffersff_tx_clkff_tx_data[31:0]ff_tx_sopff_tx_eopff_tx_rdyff_tx_wr

RGMII TransmitOn transmit, all data transfers are synchronous to both edges of tx_clk. The RGMII control signal tx_controlis asserted to indicate the

Figure 7-20: RGMII Receive in 1000 Mbpsrx_clkrx_controlrgmii_in[3:0] 00 5 D 0 5 4 5 E 5 F 5 0 6 0A frame received on the RGMII interface with a PHY er

Figure 7-22: Egress Timestamp Insert for IEEE 1588v2 PTP Packet Encapsulated in IEEE 802.3Egress Timestamp Insert, IEEE 1588v2, PTP Packet2-step Times

Memory(M9K Blocks/ M144KBlocks/MLAB Bits)LogicRegistersCombina-tional ALUTsFIFO BufferSize (Bits)SettingsMegaCoreFunction0/0/336433952721—MII/GMII Ful

Figure 7-23: Type 1 Egress Correction Field UpdateType 1 Egress Correction Field Update, 96b, IPV42-step Timestamp Request,Inputtx_egress_timestamp_re

Figure 7-24: Type 2 Egress Correction Field UpdateType 2 Egress Correction Field Update, 64b, IPV62-step Timestamp Request,Inputtx_egress_timestamp_re

Figure 7-25: Egress 2-Step OperationEgress Two-Step Operation, IEEE 1588v2, PTP Packet2-step Timestamp Request,Inputtx_egress_timestamp_request_validt

8Design Considerations2014.06.30UG-01008SubscribeSend FeedbackOptimizing Clock Resources in Multiport MAC with PCS and Embedded PMAThe following facto

Configurations(1)ClocksMAC and PCS with PMAMAC and PCSMAC OnlyNotes to Table 8-1 :1. Yes indicates that the clock is visible at the top-level design.

Figure 8-1: Clock Distribution in MAC and SGMII PCS with GXB Configuration—Optimal CaseFigure shows the optimal clock distribution scheme you can achi

Figure 8-2: Clock Distribution in MAC and 1000BASE-X PCS with GXB Configuration—Optimal CaseFigure shows the optimal clock distribution scheme you can

Figure 8-3: Clock Distribution in MAC and SGMII PCS with LVDS Configuration—Optimal CaseFigure shows the optimal clock distribution scheme you can ach

Figure 8-4: Clock Distribution in MAC and 1000BASE-X PCS with LVDS Configuration—Optimal CaseFigure shows the optimal clock distribution scheme you ca

rx_recovclkout clock must be buffered by two levels of inverter in the top level module so that it can befitted to the general I/O pins.Sharing Transc

Memory(M9K Blocks/ Mi44KBlocks/ MLAB Bits)LogicRegistersLogicElementsFIFO BufferSize (Bits)SettingsMegaCoreFunction31/0/0366656142048x32MII/GMII Full

Recommended Termination ValueWidthI/OPort Name1'b11Imagic_sleep_n1'b01Iff_tx_crc_fwdLeft open1Off_tx_septyLeft open1Otx_ff_uflowLeft open1Of

9Timing Constraints2014.06.30UG-01008SubscribeSend FeedbackAltera provides timing constraint files (.sdc) to ensure that the Triple-Speed Ethernet Meg

Figure 9-1: Triple-Speed Ethernet Timing Constraint Exampleuser_instance.vTOP.vAltera PLL10/100/1000-Mbps Ethernet MACwith 1000BASE-X/SGMIIPCS and PMA

Recommended Clock FrequencyTable 9-1: Recommended Clock Input Frequency For Each MegaCore Function VariantRecommended Frequency(MHz)ClockMegaCore Func

Recommended Frequency(MHz)ClockMegaCore Function Variant50–100CLK1000BASE-X/SGMII PCS only125REF_CLK125TBI_TX_CLK125TBI_RX_CLKTiming ConstraintsAltera

10Testbench2014.06.30UG-01008SubscribeSend FeedbackYou can use the testbench provided with the Triple-Speed Ethernet MegaCore function to exercise you

• Device under test (DUT)—Your custom MegaCore function variation• Avalon-ST Ethernet frame generator—Simulates a user application connected to the MA

• Additional checks for configurations that contain the PCS function with optional embedded PMA:• Transmit frames generated by the frame generator are

Simulation ModelThis section describes the step-by-step instructions for generating the simulation model and simulating yourdesign using the ModelSim

b. Run the following command to set up the required libraries, to compile the generated IP Functionalsimulation model, and to exercise the simulation

Memory(M20K Blocks/ MLABBits)LogicRegistersCombina-tional ALUTsFIFO BufferSize (Bits)SettingsMegaCoreFunction60/245764836535303—MII/GMII All MAC optio

11Software Programming Interface2014.06.30UG-01008SubscribeSend FeedbackDriver ArchitectureFigure 11-1: Triple-Speed Ethernet Software Driver Architec

Directory StructureStructure of the altera_triple_speed_ethernet directory.Figure 11-2: Directory StructureHALaltera_triple_speed_ethernetinctriple_sp

PHY Speed BitsSpeed (Mbps)LSBMSB0010For PHYs that do not conform to the aforementioned specifications, you can write a function to retrieve thePHY’s o

Example of PHY Instance Structuretypedef struct alt_tse_system_phy_struct { /* PHY instance *//* PHY's MDIO address */alt_32tse_phy_mdio_address;

DefinitionFile#ifndef BIGBUFSIZE#define BIGBUFSIZE 1536#endif<BSP project directory> \iniche\src\h\nios2\ipport.hNote to Table 11-2 :1. The maxi

DetailsTSE_PHY_SPEED_1000 if the PHYs common speed is 1000 Mbps.TSE_PHY_SPEED_100 if the PHYs common speed is 100 Mbps.TSE_PHY_SPEED_10 if the PHYs co

Detailspsys_mac—A pointer to the MAC structure.psys_sgdma—A pointer to the scatter-gather DMA structure.psys_mem—A pointer to the memory structure.psy

Details<triple_speed_ethernet_iniche.h>Include:The tse_mac_close() closes the Triple-Speed Ethernet driver by performing thefollowing operations

tse_mac_setGMII mode()Detailsint tse_mac_setGMIImode(np_tse_mac *pmac)Prototype:NoThread-safe:NoAvailable from ISR:<triple_speed_ethernet_iniche.h&

Detailspmac—A pointer to the MAC control interface base address.Parameter:SUCCESSReturn:ConstantsTable 11-3 lists all constants defined for the MAC re

DescriptionItemIP-TRIETHERNETOrdering Code00BD (Triple-Speed Ethernet MegaCore function)0104 (IEEE 1588v2)Product ID(s)6AF7Vendor ID(s)Altera verifies

DescriptionValueConstantConfigures the PAUSE_FWD bit.7ALTERA_TSEMAC_CMD_PAUSE_FWD_OFST0x80ALTERA_TSEMAC_CMD_PAUSE_FWD_MSKConfigures the PAUSE_IGNORE b

DescriptionValueConstantConfigures the ENA_10 bit.25ALTERA_TSEMAC_CMD_ENA_10_OFST0x2000000ALTERA_TSEMAC_CMD_ENA_10_MSKConfigures the RX_ERR_DISC bit.2

AEthernet Frame Format2014.06.30UG-01008SubscribeSend FeedbackBasic Frame FormatFigure A-1: MAC Frame Format7 octetsPREAMBLE1 octet SFD6 octets DESTIN

fields. VLAN tagging is defined by the IEEE Standard 802.1Q. VLAN tagging can identify and separate manygroups' network traffic from each other i

Pause Frame FormatA pause frame is generated by the receiving device to indicate congestion to the emitting device. If flowcontrol is supported, the e

DescriptionRegister Write or I/O Pin Assertion (1)XON_GENXOFF_GENIf the XON_GEN bit is set to 1, the XON pause frames arecontinuously generated and se

BSimulation Parameters2014.06.30UG-01008SubscribeSend FeedbackFunctionality Configuration ParametersYou can use these parameters to enable or disable

DefaultDescriptionParameter1Sets the PAD_EN bit in the command_config register. SeeCommand_Config Register (Dword Offset 0x02) onpage 6-7.TB_MACPADEN1

DefaultDescriptionParameter0x8876543322110x8866443526110xABCDEF0123130x92456545AB150x4326800102170xADB5892154390xFFEACFE3434B0xFFCCDDAA31230xADB358415

DefaultDescriptionParameter10: Disables padding.1: If the length of frames generated by the GMII/RGMII/MII Ethernetframe generator is less than the mi

ContentsAbout This MegaCore Function...1-1About This MegaCore Function...

2Getting Started with Altera IP Cores2014.06.30UG-01008SubscribeSend FeedbackIntroduction to Altera IP CoresAltera®and strategic IP partners offer a b

DefaultDescriptionParameter10: Disables gigabit operation.1: Enables gigabit operation.TB_SGMII_100000: Disables 100 Mbps operation.1: Enables 100 Mbp

CTime-of-Day (ToD) Clock2014.06.30UG-01008SubscribeSend FeedbackThe Time-of-Day (ToD) clock provides a stream of timestamps for the IEEE 1588v2 featur

Table C-2: Stratix V Performance and Resource UtilizationMemory (M20KBlocks/MLABBits)Logic RegistersCombinationalALUTsFIFO BufferSize (Bits)SettingsMe

ToD Clock Interface SignalsFigure C-1: Time-of-Day Clock Interface SignalsToD ClockAvalon-MMControlInterfaceSignalscsr_readdata[]32csr_readclkrst_ncsr

ToD Clock Avalon-ST Transmit Interface SignalsTable C-5: Avalon-ST Transmit Interface Signals for ToD ClockDescriptionWidthDirectionSignalTimestamp fr

ToD Clock Configuration Register SpaceTable C-6: ToD Clock RegistersHWResetDescriptionR/WNameDwordOffset0x0• Bits 0 to 15: High-order 16-bit second fi

HWResetDescriptionR/WNameDwordOffset0x0The drift of ToD adjusted periodically by addinga correction value as configured in this registerspace.• Bits 0

DToD Synchronizer2014.06.30UG-01008SubscribeSend FeedbackThe ToD Synchronizer provides a high accuracy synchronization of time of day from a master To

ToD Synchronizer BlockFigure D-1: Connection between ToD Synchronizer, Master ToD, Slave ToD, and Sampling Clock PLLSlave ToDtime_of_day_96b_load_vali

• 1G master and 10G (312.5 Mhz) slave—(32/63)*125 MHz or (64/315)*312.5 MHz• 10G (156.25 MHz) master and 10G (312.5 Mhz) slave—(64/63)*156.25 MHz or (

Figure 2-1: IP Core Installation Pathacdsquartus - Contains the Quartus II softwareip - Contains the Altera IP Library and third-party IP coresaltera

DescriptionValueNameA 4-bit value that defines the reset value for ananosecond of period.The default value is 4'h6 to capture 6.4ns for156.25 MHz

DescriptionWidthDirectionSignalThis signal carries the 64-bit or 96-bit formatdata for the time of day from the master ToD.The width of this signal is

EPacket Classifier2014.06.30UG-01008SubscribeSend FeedbackThe Packet Classifier decodes the packet types of incoming PTP packets and returns the decod

Packet Classifier SignalsPacket Classifier Common Clock and Reset SignalsTable E-1: Clock and Reset Signals for the Packet ClassifierDescriptionWidthD

Packet Classifier Ingress Control SignalsTable E-4: Ingress Control Signals for the Packet ClassifierDescriptionWidthDirectionSignal96-bit format of i

DescriptionWidthDirectionSignalIndicates the update for residence time.• 1: Allows update for residence timebased on decoded results.• 0: Prevents upd

Packet Classifier Timestamp Field Location SignalsThese signals must be aligned to the start of a packet.Table E-6: Timestamp Field Location Signals f

FAdditional Information2014.06.30UG-01008SubscribeSend FeedbackAdditional information about the document and Altera.ISO9001:2008Registered©2014 Altera

Document Revision HistoryChangesVersionDate• Added a link to the Altera website that provides the latest device supportinformation for Altera IP.• Add

ChangesVersionDate• Added support for Arria 10 device.• Added device family support list for IEEE 1588v2 variant.• Updated the PCS/Transceiver options

Before you beginUpgrading IP cores changes your original design files. If you have not already preserved your original sourcefiles, click Project >

ChangesVersionDate• Updated the MegaWizard Plug-In Manager flow in Getting Started withAltera IP Cores.• Added information about generating a design e

ChangesVersionDate• Added Altera IEEE 1588v2 Feature section in Chapter 4.• Added information for the following GUI parameters: Enable timestamping,En

ChangesVersionDate• Added support for Cyclone IV, Hardcopy III, and Hardcopy IV, and updatedsupport for Hardcopy II to full.• Updated chapter 1 to inc

How to Contact AlteraTable F-1: Altera Contact InformationAddressContact MethodContact(3)www.altera.com/supportWebsiteTechnical supportwww.altera.com/

Example 2-1: Upgrading IP Cores at the Command LineAlternatively, you can upgrade IP cores at the command line. To upgrade a single IP core, type thef

Figure 2-3: Quartus II IP CatalogSearch and filter IP for your target deviceDouble-click to customize, right-click for informationThe IP Catalog and p

Figure 2-4: IP Parameter EditorsView IP portand parameterdetailsApply preset parameters forspecific applicationsSpecify your IP variation nameand targ

4. In the New Project Wizard: Add Files page, select the existing design files (if any) you want to includein the project.(1)Click Next.5. In the New

Generating a design example can increase processing time.Note:You can now integrate your custom IP core instance in your design, simulate, and compile

Generated FilesThe type of files generated in your project directory and their names may vary depending on the customvariation of the MegaCore functio

DescriptionFile NameA directory containing VHDL and Verilog HDL models of theEthernet generators and monitors used by the generated testbench./testben

Ethernet MAC Options...3-2

3Parameter Settings2014.06.30UG-01008SubscribeSend FeedbackParameter SettingsYou customize the Triple-Speed Ethernet MegaCore function by specifying p

DescriptionValueNameDetermines the Ethernet-side interface of theMAC block.• MII—The only option available for 10/100Mb Small MAC core variations.• GM

• Enable MAC 10/100 half duplex support (10/100 Small MAC variations)• Align packet headers to 32-bit boundary (10/100 and 1000 Small MAC variations)T

DescriptionValueNameTurn on this option to include the logic for full-duplex flow control that includes pause framesgeneration and termination.On/OffE

Timestamp OptionsTable 3-4: Timestamp Options ParametersParameterValueNameTimestampTurn on this parameter to enable time stampingon the transmitted an

ParameterValueNameThis option is not supported in Stratix V,Arria V, Arria V GZ, and Cyclone V devices.Turn on this option to export the powerdownsign

ParameterValueNameSpecifies the channel number for the GXBtransceiver block. In a multiport MAC, thisparameter specifies the channel number for thefir

4Functional Description2014.06.30UG-01008SubscribeSend FeedbackThe Triple-Speed Ethernet MegaCore function includes the following functions:• 10/100/1

MAC ArchitectureFigure 4-1: 10/100/1000 Ethernet MAC With Internal FIFO BuffersReceiveFIFO BufferTransmitFIFO BufferConfiguration andStatisticsMDIO Ma

Figure 4-2: Multiport MAC Without Internal FIFO BuffersConfigurationandStatisticsCRC CheckPause FrameTerminationPort 0LoopbackReceiverControlTransmitt

Triple-Speed Ethernet with IEEE 1588v2 Design Example...5-1Software Requirements...

• Avalon-ST on the system side.• Avalon-ST sink port on transmit with the following properties:• Fixed data width, 8 bits, in MAC variations without i

CRC-32 field, and inserts interpacket gap (IPG) bytes. In half-duplex mode, the MAC function also detectscollision and attempts to retransmit frames w

Interpacket Gap InsertionIn full-duplex mode, the MAC function maintains the minimum number of IPG configured in thetx_ipg_length register between tra

The backoff time is a multiple of slot times. One slot is equal to a 512 bit times period. The number of thedelay slot times, before the Nth retransmi

Unicast Address CheckingWhen promiscuous mode is disabled, the MAC function only accepts unicast frames if the destinationaddress matches any of the f

ValueHash Code Bitxor multicast MAC address bits 47:405Table 4-2: Hash Code Generation—Lower 24 Bits of Destination AddressAlgorithm for generating th

Payload Pad RemovalYou can turn on padding removal by setting the PAD_EN bit in the command_config register to 1. The MACfunction removes the padding,

• Stacked VLAN tagged frames—the payload length is between 38 (0x26) and 1536 (0x0600), excluding1536.If the frame or payload length is not valid, the

Table 4-5: Transmit and Receive Nominal LatencyThe transmit and receive nominal latencies in various modes. The FIFO buffer thresholds are set to the

Receive ThresholdsFigure 4-5: Receive FIFO ThresholdsNetworkSwitch FabricFrame Buffer nFrame Buffer n - 1Frame Buffer kFrame Buffer 2Frame Buffer 1The

10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals...7-2010/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embe

DescriptionRegister NameThresholdThe number of unwritten entries in the FIFO buffer before the bufferis full. When the level of the FIFO buffer reache

Transmit ThresholdsFigure 4-6: Transmit FIFO ThresholdsNetworkSwitch FabricFrame Buffer nFrame Buffer n - 1Frame Buffer kFrame Buffer 1The remainingun

Transmit FIFO Buffer UnderflowIf the transmit FIFO buffer hits the almost-empty threshold during transmission and the FIFO buffer doesnot contain the

Remote Device CongestionWhen the MAC function receives an XOFF pause frame and the PAUSE_IGNORE bit in the command_configregister is set to 0, the MAC

Sleep ModeYou can only put a node to sleep (set SLEEP bit in the command_config register to 1 and deassert themagic_sleep_n signal) if magic packet de

MAC Error Correction CodeThe error correction code feature is implemented to memory instances in the MegaCore function. Thisfeature is capable of dete

• To trigger a hardware reset, assert the reset signal.• To trigger a software reset, set the SW_RESET bit in the command_config register to 1. The SW

For more information about the MDIO registers, refer to MAC Configuration Register Space on page 6-1.MDIO ConnectionFigure 4-9: MDIO InterfacePHYAddrM

DescriptionNameThe PHY device address (PHYAD). Up to 32 devices can be addressed. For PHY device 0, theAddr1 field is set to the value configured in t

Programmable 10/100 EthernetConnect 10/100 Ethernet PHYs to the MAC function via MII. On the receive path, connect the 25-MHz(100 Mbps) or 2.5-MHz (10

Test Flow...

Figure 4-12: 10/100/1000 PHY Interface via MII/GMIIAltera FPGAx5Unusedeth_modeset_1000set_10tx_clkm_tx_d(3:0)m_tx_enm_tx_errgm_tx_d(7:0)gm_tx_engm_tx_

You can configure the PCS function to include an embedded physical medium attachment (PMA) with a aserial transceiver or LVDS I/O and soft CDR. The PM

Figure 4-15: 1000BASE-X/SGMII PCS with Embedded PMASGMIIReceiveConverterSGMIITransmitConverterConfigurationEncapsulationDe -encapsulation&Synchron

Receive OperationThe receive operation includes comma detection, decoding, de-encapsulation, synchronization, and carriersense.Comma DetectionThe comm

When a collision happens, the collision detection state machine drives the mii_rx_col and led_col signalsto 1. You can use the led_col signal as a vis

ReceiveIn gigabit mode, the PCS and MAC functions must operate at the same rate. The transmit converter transmitseach byte from the PCS function once

Figure 4-16: Auto-Negotiation Activity (Simplified)DataLink Partner PCSLinkSynchronizationAcquiredLinkTimer= 10 ms/C/ with dev_ability register andACK

Figure 4-17: SGMII Auto-Negotiation in MAC Mode and PHY ModeSGMII PCS(MAC Mode)SGMII LinkMediumTwistedCopperPairDevice AbilityLink Partner AbilityAlte

Figure 4-18: SGMII Auto-Negotiation ActivityLink Timer= 1.6 msDataPHYSGMII PCSLinkSynchronizationAcquired/C/ with 0x00 ability/C/ with dev_ability/C/

Figure 4-19: SERDES Serialization Overviewserializationtbi_tx_d(9:0)1.25GbpsSerial Stream9 0On receive, the SERDES must serialize the TBI least signif

ToD Clock Device Family Support...C-1ToD Clock

When the PHY is in power-down state, the PCS function is in reset and any activities on the GMII transmitand the TBI receive interfaces are ignored. T

Figure 4-24: Reset Distribution in PCS with Embedded PMAPMAResetSequencerResetSynchronizerResetSynchronizerPCSresetreset_tx_clkreset_rx_clkgbx_pwrdn_i

• 10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS and embedded serial PMA without FIFO bufferin full-duplex mode• 10/100/1000-Mbps MAC with 1000BASE-X/

IEEE 1588v2 ArchitectureFigure 4-26: Overview of the IEEE 1588v2 FeatureThis figure shows only the datapaths related to the IEEE 1588v2 feature.IEEE 1

Table 4-12: Timestamp and Correction Insertion for 1-Step Clock SynchronizationThis table summarizes the timestamp and correction field insertions for

PTP Frame in IEEE 802.3Figure 4-27: PTP Frame in IEEE 8002.3flagFieldcorrectionFieldtransportSpecific | messageTypereserved | versionPTPreserved1 Octe

Figure 4-28: PTP Frame over UDP/IPv4MAC HeaderUDP HeaderIP HeaderPTP HeaderTime To LiveProtocol = 0x11Version | Internet Header LengthDifferentiated S

Figure 4-29: PTP Frame over UDP/IPv6Version | Traffic Class | Flow LabelPayload Length4 Octet2 OctetsSource IP Address16 OctetsDestination IP Address1

5Triple-Speed Ethernet with IEEE 1588v2 DesignExample2014.06.30UG-01008SubscribeSend FeedbackSoftware RequirementsAltera uses the following software t

Triple-Speed Ethernet with IEEE 1588v2 Design Example ComponentsFigure 5-1: Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Block DiagramEth

1About This MegaCore Function2014.06.30UG-01008SubscribeSend FeedbackAbout This MegaCore FunctionThe Altera®Triple-Speed Ethernet MegaCore®function is

• Avalon-MM Master Translator—provides access to the registers of the following components throughthe Avalon-MM interface:• Triple-Speed Ethernet MAC•

Creating a New Triple-Speed Ethernet MAC with IEEE 1588v2 DesignYou can use the Quartus II software to create a new Triple-Speed Ethernet MAC with IEE

The testbenches comprise the following modules:• Device under test (DUT)—the design example.• Avalon driver—uses Avalon-ST master bus functional model

• Configures the MAC. In the MAC, sets the transmit primary MAC address to EE-CC-88-CC-AA-EE,sets the speed to 1000 Mbps, enables TX and RX MAC, enabl

6Configuration Register Space2014.06.30UG-01008SubscribeSend FeedbackMAC Configuration Register SpaceUse the registers to configure the different aspe

DescriptionSectionDword OffsetTransmit and receive datapaths control register. For moreinformation about these registers, see Transmit and ReceiveComm

Base Configuration Registers (Dword Offset 0x00 – 0x17)Table 6-2 lists the base registers you can use to configure the MAC function. A software reset

HW ResetDescriptionR/WNameDwordOffset0• Bits[15:0]—16-bit pause quanta. Use this register tospecify the pause quanta to be sent to remote deviceswhen

HW ResetDescriptionR/WNameDwordOffset0Variable-length section-full threshold of the transmitFIFO buffer. Use the depth of your FIFO buffer todetermine

HW ResetDescriptionR/WNameDwordOffset0Variable-length almost-full threshold of the transmitFIFO buffer. Use the depth of your FIFO buffer todetermine

• 1000BASE-X/SGMII PCS features:• Compliance with Clause 36 of the IEEE standard 802.3.• Optional embedded PMA implemented with serial transceiver or

Command_Config Register (Dword Offset 0x02)Figure 6-1: Command_Config Register FieldsT X _E N AR X _E N AX O N _G E NE T H _S P E E DP R O M IS _E NP

DescriptionR/WNameBit(s)CRC forwarding on receive.• Set this bit to 1 to forward the CRC field to the userapplication.• Set this bit to 0 to remove th

DescriptionR/WNameBit(s)Late collision condition.• The MAC function sets this bit to 1 when it detects acollision after transmitting 64 bytes and disc

DescriptionR/WNameBit(s)Sleep mode enable. When the MAGIC_ENA bit is 1, set this bit to1 to put the MAC function to sleep and enable magic packetdetec

DescriptionR/WNameBit(s)Statistics counters reset. Set this bit to 1 to clear the statisticscounters. The MAC function clears this bit when the resets

DescriptionR/WNameDwordOffsetThe number of transmit frames with one the following errors:• FIFO overflow error• FIFO underflow error• Errors defined b

DescriptionR/WNameDwordOffsetThe number of received good and errored frames between thelength of 1024 and 1518 bytes.ROetherStatsPkts1024to1518Octets0

Table 6-5: Transmit and Receive Command RegistersDescriptionR/WNameDwordOffsetSpecifies how the MAC function processes transmit frames.When you turn o

Supplementary Address (Dword Offset 0xC0 – 0xC7)A software reset has no impact on these registers. MAC supplementary addresses are not available in 10

IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6)Table 6-7: IEEE 1588v2 MAC RegistersHW ResetDescriptionR/WNameDwordOffset0x0Clock period for timestamp a