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Parameter Name Type Required Description
ADDNSUB_MULTIPLIER_REGISTER[] String No Parameter [1, 3]. Specifies the clock signal
for the register on the corresponding
addnsub[] input. Values are UNREGISTERED,
CLOCK0, CLOCK1and CLOCK2. If the
corresponding addnsub[] port is UNUSED,
this parameter is ignored. If omitted, the
default value is UNREGISTERED.
ADDNSUB_MULTIPLIER_ACLR[] String No Parameter [1, 3]. Specifies the asynchronous
clear signal for the first register on the
corresponding addnsub[] input. Values are
NONE, ACLR0 and ACLR1. If the corresponding
addnsub[] port value is UNUSED, this
parameter is ignored. If omitted, the default
value is NONE.
PORT_ADDNSUB[] String No Parameter [1, 3]. Specifies the usage of the
corresponding addnsub[] input port. Values
are PORT_USED and PORT_UNUSED. If omitted,
the default value is PORT_UNUSED.
CHAINOUT_ADDER String No Specifies the chainout mode of the final
adder stage. Values are YES and NO. If
omitted, the default value is NO.
WIDTH_CHAININ Integer No Width of the chainin[] port. WIDTH_
CHAININ equals WIDTH_RESULT if chainin
port is used. If omitted, the default value is 1.
ACCUM_SLOAD_REGISTER String No Specifies the clock source for the first
register on the accum_sload or sload_
accum input. Values are UNREGISTERED,
CLOCK0, CLOCK1 and CLOCK2. If omitted, the
default value is UNREGISTERED .
ACCUM_SLOAD_ACLR String No Specifies the asynchronous clear source for
the first register on the accum_sload or
sload_accum input. Values are NONE, ACLR0
and ACLR1. If omitted, the default value is
NONE.
SCANOUTA_REGISTER String No Specifies the clock source for the scanouta
data bus registers. Values are UNREGISTERED,
CLOCK0, CLOCK1 and CLOCK2. If omitted, the
default value is UNREGISTERED.
SCANOUTA_ACLR String No Specifies the asynchronous clear source for
the scanouta data bus registers. Values are
NONE, ACLR0, ACLR1 and ACLR2. If omitted,
the default value is NONE.
WIDTH_C Integer No Width of the datac[] port.
WIDTH_COEF Integer No Specifies the width of the constant value
stored.
UG-01063
2014.12.19
ALTERA_MULT_ADD Parameters
6-15
ALTERA_MULT_ADD (Multiply-Adder)
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- IP Cores Function Overview 6
- Design Example Files 7
- Using the Parameter Editor 9
- UG-01063 10
- 2014.12.19 10
- Legacy parameter 12
- Upgrading IP Cores 13
- Related Information 16
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Simulating Altera Designs 18
- LPM_COUNTER (Counter) 19
- LPM_DIVIDE (Divider) 26
- LPM_MULT (Multiplier) 32
- LPM_MULT Ports 34
- LPM_MULT Parameters 35
- Decoder) 39
- ALTECC_ENCODER Features 40
- Ports (ALTECC_ENCODER) 45
- Ports (ALTECC_DECODER) 45
- Parameters (ALTECC_ENCODER) 46
- Parameters (ALTECC_DECODER) 46
- ALTERA_MULT_ADD 54
- ALTERA_MULT_ADD Parameters 65
- Coefficient Multiplier) 74
- ALTMULT_ACCUM 82
- ALTMULT_ACCUM Ports 85
- ALTMULT_ACCUM Parameters 87
- Altera Corporation 101
- Send Feedback 101
- ALTMULT_ADD (Multiply-Adder) 102
- ALTMULT_ADD 103
- Features 104
- Pre-adder 105
- Pre-adder Input Mode 106
- Pre-adder Square Mode 106
- Pre-adder Constant Mode 107
- Systolic Delay Register 108
- Pre-load Constant 111
- Double Accumulator 111
- Verilog HDL Prototype 112
- VHDL Component Declaration 112
- VHDL LIBRARY_USE Declaration 113
- ALTMULT_ADD Ports 113
- ALTMULT_ADD Parameters 115
- Parameter Name Type Requi 116
- Description 116
- Subscribe 138
- Complex Multiplication 139
- Canonical Representation 139
- Conventional Representation 140
- ALTMULT_COMPLEX Ports 143
- ALTMULT_COMPLEX Parameters 143
- ALTSQRT (Integer Square Root) 147
- Parameters 149
- PARALLEL_ADD (Parallel Adder) 151
- Document Revision History 156
- Date Version Changes 157
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