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LPM_MULT (Multiplier)
4
2014.12.19
UG-01063
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The LPM_MULT megafunction implements a multiplier to multiply two input data values to produce a
product as an output.
The following figure shows the ports for the LPM_MULT megafunction.
Figure 4-1: LPM_Mult Ports
clock
dataa[]
inst
LPM_MULT
datab[]
aclr
result[]
clken
Features
The LPM_MULT megafunction offers the following features:
• Generates a multiplier that multiplies two input data values
• Supports data width of 1–256 bits
• Supports signed and unsigned data representation format
• Supports area or speed optimization
• Supports pipelining with configurable output latency
• Provides an option for implementation in dedicated digital signal processing (DSP) block circuitry or
logic elements (LEs)
Note:
When building multipliers larger than the natively supported size there may/will be a perform‐
ance impact resulting from the cascading of the DSP blocks.
• Supports optional asynchronous clear and clock enable input ports
Resource Utilization and Performance
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- IP Cores Function Overview 6
- Design Example Files 7
- Using the Parameter Editor 9
- UG-01063 10
- 2014.12.19 10
- Legacy parameter 12
- Upgrading IP Cores 13
- Related Information 16
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Simulating Altera Designs 18
- LPM_COUNTER (Counter) 19
- LPM_DIVIDE (Divider) 26
- LPM_MULT (Multiplier) 32
- LPM_MULT Ports 34
- LPM_MULT Parameters 35
- Decoder) 39
- ALTECC_ENCODER Features 40
- Ports (ALTECC_ENCODER) 45
- Ports (ALTECC_DECODER) 45
- Parameters (ALTECC_ENCODER) 46
- Parameters (ALTECC_DECODER) 46
- ALTERA_MULT_ADD 54
- ALTERA_MULT_ADD Parameters 65
- Coefficient Multiplier) 74
- ALTMULT_ACCUM 82
- ALTMULT_ACCUM Ports 85
- ALTMULT_ACCUM Parameters 87
- Altera Corporation 101
- Send Feedback 101
- ALTMULT_ADD (Multiply-Adder) 102
- ALTMULT_ADD 103
- Features 104
- Pre-adder 105
- Pre-adder Input Mode 106
- Pre-adder Square Mode 106
- Pre-adder Constant Mode 107
- Systolic Delay Register 108
- Pre-load Constant 111
- Double Accumulator 111
- Verilog HDL Prototype 112
- VHDL Component Declaration 112
- VHDL LIBRARY_USE Declaration 113
- ALTMULT_ADD Ports 113
- ALTMULT_ADD Parameters 115
- Parameter Name Type Requi 116
- Description 116
- Subscribe 138
- Complex Multiplication 139
- Canonical Representation 139
- Conventional Representation 140
- ALTMULT_COMPLEX Ports 143
- ALTMULT_COMPLEX Parameters 143
- ALTSQRT (Integer Square Root) 147
- Parameters 149
- PARALLEL_ADD (Parallel Adder) 151
- Document Revision History 156
- Date Version Changes 157
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