Altera Integer Arithmetic IP Manuale Utente Pagina 145
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Parameter Name Type Required Description
WIDTH_B Integer Yes Specifies the width of the datab_
real[] and datab_imag[] ports. Value
must be 256 bits or less. If omitted, the
default value is 18.
WIDTH_RESULT Integer Yes Specifies the width of the result_
real[] and result_imag[] ports.
Value must be 256 bits or less. If
omitted, the default value is 36.
INTENDED_DEVICE_FAMILY String No This parameter is used for modeling
and behavioral simulation purposes.
Create the ALTMULT_COMPLEX
megafunction with the MegaWizard
Plug-in Manager to calculate the value
for this parameter.
LPM_HINT String No
When you instantiate a library of
parameterized modules (LPM) function
in a VHDL Design File (.vhd), you
must use the LPM_HINT parameter to
specify an Altera-specific parameter.
For example: LPM_HINT = "CHAIN_
SIZE = 8, ONE_INPUT_IS_CONSTANT
= YES"
The default value is UNUSED.
LPM_TYPE String No Identifies the library of parameterized
modules (LPM) entity name in VHDL
design files.
Design Example: Multiplication of 8-bit Complex Numbers Using
Canonical Representation
This design example uses the ALTMULT_COMPLEX megafunction to implement a complex multiplier
with an 8-bit input data width using the canonical representation. This example uses the MegaWizard
Plug-In Manager in the Quartus II software.
The following design files can be found in altmult_complex_DesignExample.zip:
complex_canonical.qar (archived Quartus II design files)
altmult_complex_ex_msim (ModelSim-Altera files)
Understanding the Simulation Results
10-8
Design Example: Multiplication of 8-bit Complex Numbers Using Canonical
Representation
UG-01063
2014.12.19
Altera Corporation
ALTMULT_COMPLEX (Complex Multiplier)
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- IP Cores Function Overview 6
- Design Example Files 7
- Using the Parameter Editor 9
- UG-01063 10
- 2014.12.19 10
- Legacy parameter 12
- Upgrading IP Cores 13
- Related Information 16
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Simulating Altera Designs 18
- LPM_COUNTER (Counter) 19
- LPM_DIVIDE (Divider) 26
- LPM_MULT (Multiplier) 32
- LPM_MULT Ports 34
- LPM_MULT Parameters 35
- Decoder) 39
- ALTECC_ENCODER Features 40
- Ports (ALTECC_ENCODER) 45
- Ports (ALTECC_DECODER) 45
- Parameters (ALTECC_ENCODER) 46
- Parameters (ALTECC_DECODER) 46
- ALTERA_MULT_ADD 54
- ALTERA_MULT_ADD Parameters 65
- Coefficient Multiplier) 74
- ALTMULT_ACCUM 82
- ALTMULT_ACCUM Ports 85
- ALTMULT_ACCUM Parameters 87
- Altera Corporation 101
- Send Feedback 101
- ALTMULT_ADD (Multiply-Adder) 102
- ALTMULT_ADD 103
- Features 104
- Pre-adder 105
- Pre-adder Input Mode 106
- Pre-adder Square Mode 106
- Pre-adder Constant Mode 107
- Systolic Delay Register 108
- Pre-load Constant 111
- Double Accumulator 111
- Verilog HDL Prototype 112
- VHDL Component Declaration 112
- VHDL LIBRARY_USE Declaration 113
- ALTMULT_ADD Ports 113
- ALTMULT_ADD Parameters 115
- Parameter Name Type Requi 116
- Description 116
- Subscribe 138
- Complex Multiplication 139
- Canonical Representation 139
- Conventional Representation 140
- ALTMULT_COMPLEX Ports 143
- ALTMULT_COMPLEX Parameters 143
- ALTSQRT (Integer Square Root) 147
- Parameters 149
- PARALLEL_ADD (Parallel Adder) 151
- Document Revision History 156
- Date Version Changes 157
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