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5–18 Chapter 5: Functional Description—ALTMEMPHY
Block Description
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Clock and reset management for full-rate designs is similar to half-rate support (see
Table 5–4 on page 5–17). The PLL is configured exactly in the same way as for
half-rate support. The
mem_clk_2x
output acts as the PHY full-rate clock. Also, instead
of going through the I/O clock divider, the
resync_clk_2x
output is now directly
connected to the resynchronization registers. The rest of the PLL outputs are
connected in the same way as for half-rate support.
Half-rate and
full-rate
write_clk_
2x
C3 –90 Full-Rate Dual regional
Clocks the data out of the
double data rate
input/output (DDIO) pins
in advance of the DQS
strobe (or equivalent). As
a result, its phase leads
that of the
mem_clk_2x
clock by 90°.
Half-rate and
full-rate
resync_clk_
2x
C4 Calibrated Full-Rate Dual regional
This clock feeds the I/O
clock divider that then
clocks the
resynchronization
registers after the capture
registers. Its phase is
adjusted in the calibration
process. You can use an
inverted version of this
clock for postamble
clocking.
Half-rate and
full-rate
measure_clk_1x
(2)
C5 Calibrated Half-Rate Dual regional
This clock is for VT
tracking. This free-running
clock measures relative
phase shifts between the
internal clock(s) and those
being fed back through a
mimic path. As a result,
the ALTMEMPHY
megafunction can track VT
effects on the FPGA and
compensate for the
effects.
Half-rate and
full-rate
ac_clk_1x
C6
Set in the
GUI
Half-Rate Dual regional
Address and command
clock.
Notes to Table 5–4:
(1) In full-rate designs a
_1x
clock may run at full-rate clock rate.
(2) This clock should be of the same clock network clock as the
resync_clk_2x
clock.
Table 5–4. DDR2 SDRAM Clocking in Stratix IV and Stratix III Devices (Part 2 of 2)
Design Rate Clock Name (1)
Postscale
Counter
Phase
(Degrees)
Clock Rate
Clock Network
Type
Notes
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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