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- Pagina / 140
- Indice
- SEGNALIBRI
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
Sommario
101 Innovation DriveSan Jose, CA 95134www.altera.com EMI_DDR_UG-3.0 Section I. DDR and DDR2 SDRAM Controllers withALTMEMPHY IP User GuideExternal Memo
1–4 Chapter 1: About This IPUnsupported FeaturesExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and DDR2 SDRAM
6–6 Chapter 6: Functional Description—High-Performance Controller IIController Features DescriptionsExternal Memory Interface Handbook Volume 3 June 2
Chapter 6: Functional Description—High-Performance Controller II 6–7Controller Features DescriptionsJune 2011 Altera Corporation External Memory Inter
6–8 Chapter 6: Functional Description—High-Performance Controller IIController Features DescriptionsExternal Memory Interface Handbook Volume 3 June 2
Chapter 6: Functional Description—High-Performance Controller II 6–9External InterfacesJune 2011 Altera Corporation External Memory Interface Handbook
6–10 Chapter 6: Functional Description—High-Performance Controller IIExternal InterfacesExternal Memory Interface Handbook Volume 3 June 2011 Altera C
Chapter 6: Functional Description—High-Performance Controller II 6–11Top-Level Signals DescriptionJune 2011 Altera Corporation External Memory Interfa
6–12 Chapter 6: Functional Description—High-Performance Controller IITop-Level Signals DescriptionExternal Memory Interface Handbook Volume 3 June 201
Chapter 6: Functional Description—High-Performance Controller II 6–13Top-Level Signals DescriptionJune 2011 Altera Corporation External Memory Interfa
6–14 Chapter 6: Functional Description—High-Performance Controller IITop-Level Signals DescriptionExternal Memory Interface Handbook Volume 3 June 201
Chapter 6: Functional Description—High-Performance Controller II 6–15Top-Level Signals DescriptionJune 2011 Altera Corporation External Memory Interfa
Chapter 1: About This IP 1–5Resource UtilizationJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM
6–16 Chapter 6: Functional Description—High-Performance Controller IITop-Level Signals DescriptionExternal Memory Interface Handbook Volume 3 June 201
Chapter 6: Functional Description—High-Performance Controller II 6–17Sequence of OperationsJune 2011 Altera Corporation External Memory Interface Hand
6–18 Chapter 6: Functional Description—High-Performance Controller IISequence of OperationsExternal Memory Interface Handbook Volume 3 June 2011 Alter
Chapter 6: Functional Description—High-Performance Controller II 6–19Example Top-Level FileJune 2011 Altera Corporation External Memory Interface Hand
6–20 Chapter 6: Functional Description—High-Performance Controller IIExample Top-Level FileExternal Memory Interface Handbook Volume 3 June 2011 Alter
Chapter 6: Functional Description—High-Performance Controller II 6–21Example Top-Level FileJune 2011 Altera Corporation External Memory Interface Hand
6–22 Chapter 6: Functional Description—High-Performance Controller IIRegister MapsExternal Memory Interface Handbook Volume 3 June 2011 Altera Corpora
Chapter 6: Functional Description—High-Performance Controller II 6–23Register MapsJune 2011 Altera Corporation External Memory Interface Handbook Volu
6–24 Chapter 6: Functional Description—High-Performance Controller IIRegister MapsExternal Memory Interface Handbook Volume 3 June 2011 Altera Corpora
Chapter 6: Functional Description—High-Performance Controller II 6–25Register MapsJune 2011 Altera Corporation External Memory Interface Handbook Volu
1–6 Chapter 1: About This IPSystem RequirementsExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and DDR2 SDRAM C
6–26 Chapter 6: Functional Description—High-Performance Controller IIRegister MapsExternal Memory Interface Handbook Volume 3 June 2011 Altera Corpora
Chapter 6: Functional Description—High-Performance Controller II 6–27Register MapsJune 2011 Altera Corporation External Memory Interface Handbook Volu
6–28 Chapter 6: Functional Description—High-Performance Controller IIRegister MapsExternal Memory Interface Handbook Volume 3 June 2011 Altera Corpora
June 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide7. Laten
7–2 Chapter 7: LatencyExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY
Chapter 7: Latency 7–3June 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY
7–4 Chapter 7: LatencyExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY
Chapter 7: Latency 7–5June 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY
7–6 Chapter 7: LatencyExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY
June 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide8. Timin
Chapter 1: About This IP 1–7Installation and LicensingJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2
8–2 Chapter 8: Timing DiagramsDDR and DDR2 High-Performance Controllers IIExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSect
Chapter 8: Timing Diagrams 8–3DDR and DDR2 High-Performance Controllers IIJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Sect
8–4 Chapter 8: Timing DiagramsDDR and DDR2 High-Performance Controllers IIExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSect
Chapter 8: Timing Diagrams 8–5DDR and DDR2 High-Performance Controllers IIJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Sect
8–6 Chapter 8: Timing DiagramsDDR and DDR2 High-Performance Controllers IIExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSect
Chapter 8: Timing Diagrams 8–7DDR and DDR2 High-Performance Controllers IIJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Sect
8–8 Chapter 8: Timing DiagramsDDR and DDR2 High-Performance Controllers IIExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSect
Chapter 8: Timing Diagrams 8–9DDR and DDR2 High-Performance Controllers IIJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Sect
8–10 Chapter 8: Timing DiagramsDDR and DDR2 High-Performance Controllers IIExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSec
June 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User GuideAddition
1–8 Chapter 1: About This IPInstallation and LicensingExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and DDR2
Info–2 Chapter :Typographic ConventionsExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and DDR2 SDRAM Controlle
June 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide2. Getti
2–2 Chapter 2: Getting StartedSOPC Builder FlowExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and DDR2 SDRAM C
Chapter 2: Getting Started 2–3SOPC Builder FlowJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM C
2–4 Chapter 2: Getting StartedQsys FlowExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and DDR2 SDRAM Controlle
Chapter 2: Getting Started 2–5Qsys FlowJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM Controlle
External Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide© 2011 A
2–6 Chapter 2: Getting StartedMegaWizard Plug-In Manager FlowExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR an
Chapter 2: Getting Started 2–7HardCopy GuidelinesJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM
2–8 Chapter 2: Getting StartedGenerated FilesExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and DDR2 SDRAM Con
Chapter 2: Getting Started 2–9Generated FilesJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM Con
2–10 Chapter 2: Getting StartedGenerated FilesExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and DDR2 SDRAM Co
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2–12 Chapter 2: Getting StartedGenerated FilesExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and DDR2 SDRAM Co
June 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide3. Param
3–2 Chapter 3: Parameter SettingsALTMEMPHY Parameter SettingsExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR an
Chapter 3: Parameter Settings 3–3ALTMEMPHY Parameter SettingsJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR an
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3–4 Chapter 3: Parameter SettingsALTMEMPHY Parameter SettingsExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR an
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Chapter 3: Parameter Settings 3–7ALTMEMPHY Parameter SettingsJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR an
3–8 Chapter 3: Parameter SettingsALTMEMPHY Parameter SettingsExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR an
Chapter 3: Parameter Settings 3–9ALTMEMPHY Parameter SettingsJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR an
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3–14 Chapter 3: Parameter SettingsDDR or DDR2 SDRAM Controller with ALTMEMPHY Parameter SettingsExternal Memory Interface Handbook Volume 3 June 2011
Chapter 3: Parameter Settings 3–15DDR or DDR2 SDRAM Controller with ALTMEMPHY Parameter SettingsJune 2011 Altera Corporation External Memory Interface
3–16 Chapter 3: Parameter SettingsDDR or DDR2 SDRAM Controller with ALTMEMPHY Parameter SettingsExternal Memory Interface Handbook Volume 3 June 2011
June 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide4. Compi
4–2 Chapter 4: Compiling and SimulatingCompiling the DesignExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and
Chapter 4: Compiling and Simulating 4–3Compiling the DesignJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and
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June 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide5. Funct
5–2 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR
Chapter 5: Functional Description—ALTMEMPHY 5–3Block DescriptionJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR
Contents vJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Gui
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Chapter 5: Functional Description—ALTMEMPHY 5–5Block DescriptionJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR
5–6 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR
Chapter 5: Functional Description—ALTMEMPHY 5–7Block DescriptionJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR
5–8 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR
Chapter 5: Functional Description—ALTMEMPHY 5–9Block DescriptionJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR
5–10 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DD
Chapter 5: Functional Description—ALTMEMPHY 5–11Block DescriptionJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DD
5–12 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DD
Chapter 5: Functional Description—ALTMEMPHY 5–13Block DescriptionJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DD
vi ContentsExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Gu
5–14 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DD
Chapter 5: Functional Description—ALTMEMPHY 5–15Block DescriptionJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DD
5–16 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DD
Chapter 5: Functional Description—ALTMEMPHY 5–17Block DescriptionJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DD
5–18 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DD
Chapter 5: Functional Description—ALTMEMPHY 5–19Block DescriptionJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DD
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Chapter 5: Functional Description—ALTMEMPHY 5–21Block DescriptionJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DD
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Chapter 5: Functional Description—ALTMEMPHY 5–23Block DescriptionJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DD
June 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide1. About
5–24 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DD
Chapter 5: Functional Description—ALTMEMPHY 5–25Block DescriptionJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DD
5–26 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DD
Chapter 5: Functional Description—ALTMEMPHY 5–27ALTMEMPHY SignalsJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DD
5–28 Chapter 5: Functional Description—ALTMEMPHYALTMEMPHY SignalsExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DD
Chapter 5: Functional Description—ALTMEMPHY 5–29ALTMEMPHY SignalsJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DD
5–30 Chapter 5: Functional Description—ALTMEMPHYALTMEMPHY SignalsExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DD
Chapter 5: Functional Description—ALTMEMPHY 5–31ALTMEMPHY SignalsJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DD
5–32 Chapter 5: Functional Description—ALTMEMPHYALTMEMPHY SignalsExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DD
Chapter 5: Functional Description—ALTMEMPHY 5–33ALTMEMPHY SignalsJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DD
1–2 Chapter 1: About This IPRelease InformationExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSection I. DDR and DDR2 SDRAM C
5–34 Chapter 5: Functional Description—ALTMEMPHYPHY-to-Controller InterfacesExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSe
Chapter 5: Functional Description—ALTMEMPHY 5–35PHY-to-Controller InterfacesJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Se
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Chapter 5: Functional Description—ALTMEMPHY 5–37PHY-to-Controller InterfacesJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Se
5–38 Chapter 5: Functional Description—ALTMEMPHYPHY-to-Controller InterfacesExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSe
Chapter 5: Functional Description—ALTMEMPHY 5–39PHY-to-Controller InterfacesJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Se
5–40 Chapter 5: Functional Description—ALTMEMPHYPHY-to-Controller InterfacesExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSe
Chapter 5: Functional Description—ALTMEMPHY 5–41PHY-to-Controller InterfacesJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Se
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Chapter 5: Functional Description—ALTMEMPHY 5–43Using a Custom ControllerJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Secti
Chapter 1: About This IP 1–3FeaturesJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM Controllers
5–44 Chapter 5: Functional Description—ALTMEMPHYUsing a Custom ControllerExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSecti
Chapter 5: Functional Description—ALTMEMPHY 5–45Using a Custom ControllerJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Secti
5–46 Chapter 5: Functional Description—ALTMEMPHYUsing a Custom ControllerExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSecti
Chapter 5: Functional Description—ALTMEMPHY 5–47Using a Custom ControllerJune 2011 Altera Corporation External Memory Interface Handbook Volume 3Secti
5–48 Chapter 5: Functional Description—ALTMEMPHYUsing a Custom ControllerExternal Memory Interface Handbook Volume 3 June 2011 Altera CorporationSecti
June 2011 Altera Corporation External Memory Interface Handbook Volume 3Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide6. Funct
6–2 Chapter 6: Functional Description—High-Performance Controller IIMemory Controller ArchitectureExternal Memory Interface Handbook Volume 3 June 201
Chapter 6: Functional Description—High-Performance Controller II 6–3Memory Controller ArchitectureJune 2011 Altera Corporation External Memory Interfa
6–4 Chapter 6: Functional Description—High-Performance Controller IIController Features DescriptionsExternal Memory Interface Handbook Volume 3 June 2
Chapter 6: Functional Description—High-Performance Controller II 6–5Controller Features DescriptionsJune 2011 Altera Corporation External Memory Inter
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