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Example 3-1: Control Word Retrieval Example
To retrieve the vendor-specific portion of a control word in the most recent received hyperframe,
perform the following steps:
1. Identify the indices for the vendor-specific portion of the transmit control table, using the
formula X = Ns + 64 + Xs.
In the example, Ns = 16 and Xs = 0, 1, 2, and 3. Therefore, the indices to be read are 16, 80,
144, and 208.
2. For each value X in 16, 80, 144, and 208, perform the following steps:
a. Write the value X to the rx_ctrl_x field of the CTRL_INDEX register.
b. Reset the rx_ctrl_seq field of the CTRL_INDEX register to the value of zero.
c. In the following cpu_clk cycle, read the first 32-bit section of the control word from the
RX_CTRL register.
d. If the CPRI line bit rate is greater than 2.4576 Gbps, increment the rx_ctrl_seq field of
the CTRL_INDEX register to the value of 1 and in the following cpu_clk cycle, read the
second 32-bit section of the #Z.X control word from the RX_CTRL register.
e. If the CPRI line bit rate is greater than 4.9152 Gbps, increment the rx_ctrl_seq field of
the CTRL_INDEX register to the value of 2 and in the following cpu_clk cycle, read the third
32-bit section of the #Z.X control word from the RX_CTRL register.
f. If the CPRI line bit rate is greater than 6.144 Gbps, increment the rx_ctrl_seq field of the
CTRL_INDEX register to the value of 3 and in the following cpu_clk cycle, read the fourth
32-bit section of the #Z.X control word from the RX_CTRL register.
g. If the CPRI line bit rate is 10.1376 Gbps, increment the rx_ctrl_seq field of the
CTRL_INDEX register to the value of 4 and in the following cpu_clk cycle, read the fifth 32-
bit section of the #Z.X control word (the real-time vendor specific bytes) from the RX_CTRL
register.
Writing the Hyperframe Control Words
A control transmit table contains one entry for each of the 256 control words in the current hyperframe.
Each control transmit table entry contains a control word and an enable bit. As the frame is created, if a
control word entry is enabled, and the global tx_ctrl_insert_en bit in the L1_CONFIG register is set, the
IP core writes the appropriate control transmit table entry to the CPRI frame's control word.
You write to a control transmit table entry through the TX_CTRL register. This register access method
requires that you write the control word in 32-bit sections. Use the tx_ctrl_seq field of the CTRL_INDEX
register to specify the 32-bit section you are currently writing to the TX_CTRL register.
To write a control word in the control transmit table, perform the following steps:
1. Write the control word number X to the tx_ctrl_x field of the CTRL_INDEX register.
2. Reset the tx_ctrl_seq field of the CTRL_INDEX register to the value of zero.
3. Write the first 32-bit section of the next intended #Z.X control word to the TX_CTRL register.
4. If the CPRI line bit rate is greater than 2.4576 Gbps, increment the tx_ctrl_seq field of the
CTRL_INDEX register to the value of 1 and write the second 32-bit section of the next intended #Z.X
control word to the TX_CTRL register.
5. If the CPRI line bit rate is greater than 4.9152 Gbps, increment the tx_ctrl_seq field of the
CTRL_INDEX register to the value of 2 and write the third 32-bit section of the next intended #Z.X
control word to the TX_CTRL register.
UG-01156
2014.08.18
Writing the Hyperframe Control Words
3-39
Functional Description
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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