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Property CPRI v6.0 IP Core (Initial Release) CPRI IP Core
Ethernet MAC Includes Ethernet PCS block that
communicates with user logic
through an IEEE 802.3 100BASE-X
100Mbps MII.
Optionally includes an Ethernet
MAC block that communicates
with user logic through registers.
If you do not include the
Ethernet MAC, user logic can
communicate with the internal
Ethernet PCS block through an
MII-like interface.
HDLC Supports optional HDLC serial
direct connection to Layer 1.
Optionally includes an HDLC
block that communicates with
user logic through registers.
Direct access to CPRI frame Supports AUX interface for direct
access to full CPRI frame, with
optional specified latency. Also
supports individual interfaces for
direct access to I/Q data bytes only,
to Ctrl-AxC bytes only, to VSS bytes
only, and for 10.1376 Gbps
variations, to RTVS bytes only. You
can configure any combination of
these interfaces.
Optionally supports register access
to all control words in CPRI frame.
Supports AUX interface for
direct access to full CPRI frame.
Optionally supports register
access to all control words in
CPRI frame.
I/Q Mapping Supports direct IQ interface to
access the I/Q bytes in the CPRI
frame.
Optionally includes an I/Q
mapper that supports certain
wireless standards. For direct
access to IQ data in the CPRI
frame, only the AUX interface is
available.
Start-Up Sequence State
Machine
Optionally includes a state machine
that controls the start-up sequence.
Optionally includes negotiation of
protocol version and Layer 2
Control and Management rates.
Requires that software control
start-up sequence, including
negotiation of protocol version
and Layer 2 Control and
Management rates.
Debug and Alarm Signals Optional additional debug interface
and optional interface for access to
all five Z.130.0 alarms.
Signals to control and monitor
Z.130.0 reset requests.
Related Information
• CPRI MegaCore Function User Guide
For detailed information about changes to top-level interfaces in different versions of the legacy CPRI
IP core, refer to the Document Revision History in the Additional Information chapter.
A-2
Differences Between CPRI v6.0 IP Core and CPRI IP Core
UG-01156
2014.08.18
Altera Corporation
Differences Between CPRI v6.0 IP Core and CPRI IP Core
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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