Altera Designing With Low-Level Primitives Manuale Utente

101 Innovation DriveSan Jose, CA 95134(408) 544-7000www.altera.comDesigning with Low-Level PrimitivesUser GuideSoftware Version 7.1Document Version: 3

1–4 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007Low-Level Primitive ExamplesFigure 1–1. Logic Merged During the Process

Altera Corporation 1–5April 2007 Designing with Low-Level Primitives User GuideLow-Level Primitive DesignIn Example 1–3, the address decoder logic is

1–6 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007Low-Level Primitive ExamplesFigure 1–2. LCELL Primitive InstantiationsU

Altera Corporation 1–7April 2007 Designing with Low-Level Primitives User GuideLow-Level Primitive DesignFor detailed specifications of the primitive

1–8 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007Low-Level Primitive ExamplesInferring Registers Using HDL CodeTo make t

Altera Corporation 1–9April 2007 Designing with Low-Level Primitives User GuideLow-Level Primitive DesignThe sclr signal is not inferred by Quartus I

1–10 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007Low-Level Primitive ExamplesInferring RAM Functions from HDL CodeTo in

Altera Corporation 1–11April 2007 Designing with Low-Level Primitives User GuideLow-Level Primitive DesignExample 1–6. A 32, 8-Bit Word Single-Port M

1–12 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007Low-Level Primitive ExamplesExample 1–7 shows a Verilog example for a

Altera Corporation 1–13April 2007 Designing with Low-Level Primitives User GuideLow-Level Primitive DesignLook-Up Table Buffer PrimitivesThe look-up

Copyright © 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-ig

1–14 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007Low-Level Primitive ExamplesExample 1–9 is a more complex example usin

Altera Corporation 1–15April 2007 Designing with Low-Level Primitives User GuideLow-Level Primitive DesignExample 1–10 uses the LUT primitive to crea

1–16 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007Low-Level Primitive Examples

Altera Corporation 2–1April 20072. Primitive ReferencePrimitivesUsing primitives with HDL is an efficient way to make assignments to your design wi

2–2 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007Primitivesthe input and output ports and the parameters associated with

Altera Corporation 2–3April 2007 Designing with Low-Level Primitives User GuidePrimitive ReferenceExample 2–2 shows a VHDL component declaration for

2–4 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007PrimitivesTable 2–2. ALT_OUTBUF Ports & ParametersPort/Parameter De

Altera Corporation 2–5April 2007 Designing with Low-Level Primitives User GuidePrimitive ReferenceExample 2–3 shows a Verilog HDL example of an ALT_O

2–6 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007PrimitivesALT_OUTBUF_TRI The primitive allows you to make a location as

Altera Corporation 2–7April 2007 Designing with Low-Level Primitives User GuidePrimitive ReferenceTable 2–3. ALT_OUTBUF_TRI Ports & ParametersPor

Altera Corporation iiiContentsAbout this User Guide ... vHow to Contact

2–8 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007PrimitivesALT_IOBUFThe primitive allows you to make a location assignme

Altera Corporation 2–9April 2007 Designing with Low-Level Primitives User GuidePrimitive ReferenceTable 2–4. ALT_IOBUF Ports and ParametersPort/Param

2–10 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007PrimitivesExample 2–8. ALT_IOBUF Primitive Component Declaration, VHDL

Altera Corporation 2–11April 2007 Designing with Low-Level Primitives User GuidePrimitive ReferenceALT_INBUF_DIFFThis primitive allows you to name an

2–12 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007PrimitivesExample 2–9 shows a VHDL component instantiation example of

Altera Corporation 2–13April 2007 Designing with Low-Level Primitives User GuidePrimitive ReferenceALT_OUTBUF_DIFFThis primitive allows you to name a

2–14 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007Primitivesthe default. Assigning –1 to slew_rate is equivalent to not

Altera Corporation 2–15April 2007 Designing with Low-Level Primitives User GuidePrimitive ReferenceTable 2–7 lists the ports and parameters of the AL

2–16 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007PrimitivesExample 2–11. ALT_OUTBUF_TRI_DIFF Primitive Instantiation, V

Altera Corporation 2–17April 2007 Designing with Low-Level Primitives User GuidePrimitive ReferenceExample 2–12. ALT_OUTBUF_TRI_DIFF Primitive, VHDL

iv Altera CorporationDesigning with Low-Level Primitives User GuideContents

2–18 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007Primitives inst : ALT_OUTBUF_TRI_DIFFgeneric map ( IO_STANDARD =

Altera Corporation 2–19April 2007 Designing with Low-Level Primitives User GuidePrimitive ReferenceALT_IOBUF_DIFFThis primitive allows you to name an

2–20 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007PrimitivesEach parameter except slew_rate also accepts the value “none

Altera Corporation 2–21April 2007 Designing with Low-Level Primitives User GuidePrimitive ReferenceExample 2–13. ALT_IOBUF_DIFF Primitive, VHDL Compo

2–22 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007PrimitivesExample 2–14. ALT_IOBUF_DIFF Primitive Instantiation, Verilo

Altera Corporation 2–23April 2007 Designing with Low-Level Primitives User GuidePrimitive ReferenceEach parameter except slew_rate also accepts the v

2–24 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007PrimitivesExample 2–15 shows an example of a Verilog HDL primitive ins

Altera Corporation 2–25April 2007 Designing with Low-Level Primitives User GuidePrimitive ReferenceExample 2–16. ALT_BIDIR_DIFF Primitive, VHDL Compo

2–26 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007PrimitivesEach parameter except slew_rate also accepts the value “none

Altera Corporation 2–27April 2007 Designing with Low-Level Primitives User GuidePrimitive ReferenceExample 2–17. ALT_BIDIR_BUF Primitive, VHDL Compon

Altera Corporation vApril 2007 Designing with Low-Level Primitives User GuideAbout this User GuideDocument Revision HistoryThe table below shows the

2–28 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007PrimitivesExample 2–19 shows a VHDL component declaration for an LCELL

Altera Corporation 2–29April 2007 Designing with Low-Level Primitives User GuidePrimitive ReferenceExample 2–21 shows a VHDL component declaration fo

2–30 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007PrimitivesThe CARRY primitive is supported for backward-compatibility

Altera Corporation 2–31April 2007 Designing with Low-Level Primitives User GuidePrimitive Reference A CASCADE primitive cannot feed an OUTPUT pin pr

2–32 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007PrimitivesExample 2–26. LUT_INPUT Primitive Instantiation, Verilog HDL

Altera Corporation 2–33April 2007 Designing with Low-Level Primitives User GuidePrimitive ReferenceSynthesis AttributesUsing synthesis attributes in

2–34 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007Synthesis Attributes

vi Altera CorporationDesigning with Low-Level Primitives User Guide April 2007Typographic ConventionsTypographic ConventionsThis document uses the ty

Altera Corporation 1–1April 20071. Low-Level PrimitiveDesignIntroduction Your hardware description language (HDL) coding style can have a significa

1–2 Altera CorporationDesigning with Low-Level Primitives User Guide April 2007Low-Level Primitive ExamplesExample 1–1 is a small Verilog example that

Altera Corporation 1–3April 2007 Designing with Low-Level Primitives User GuideLow-Level Primitive DesignIn Example 1–2, the LCELL primitive separate