Altera Designing With Low-Level Primitives Manuale Utente Scaricare il pdf (Pagina 11)

Altera Corporation 1–5

April 2007 Designing with Low-Level Primitives User Guide

Low-Level Primitive Design

In Example 1–3, the address decoder logic is not merged with the

registers in the design.

Example 1–3. Address Decoder Logic Not Merged with Registers

module comb_logic_with_lcells(

clk,

addr,

data,

dataout

);

input clk;

input[3:0] addr;

input [2:0] data;

output [2:0] dataout;

reg [2:0] dataout;

wire temp_0;

wire temp_1;

wire temp_2;

wire temp_3;

wire temp_4;

wire temp_5;

wire temp_6;

wire temp_7;

wire temp_8;

wire temp_9;

assign temp_1 = addr[0] & addr[1] & addr[2] & addr[3];

assign temp_3 = temp_4 & addr[0];

assign temp_8 = temp_5 & data[0];

assign temp_9 = temp_6 & data[1];

assign temp_0 = temp_7 & data[2];

assign temp_4 = addr[1] & addr[2] & addr[3];

assign temp_2 = addr[3] & addr[2] & addr[1] & addr[0];

lcell inst1(.in(temp_1),

.out(temp_6));

lcell inst2(.in(temp_2),

.out(temp_7));

lcell inst3(.in(temp_3),

.out(temp_5));

always@(posedge clk)

begin

dataout[2] <= temp_0;

end

always@(posedge clk)

begin

dataout[0] <= temp_8;

end

always@(posedge clk)

begin

dataout[1] <= temp_9;

end

endmodule

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