Altera Designing With Low-Level Primitives Manuale Utente Scaricare il pdf (Pagina 17)

Altera Corporation 1–11

April 2007 Designing with Low-Level Primitives User Guide

Low-Level Primitive Design

Example 1–6. A 32, 8-Bit Word Single-Port Memory Function, Verilog

altsyncramalt syncram_component (

.wren_a (wren),

.clock0 (clock),

.address_a (wraddress),

.address_b (rdaddress),

.data_a (data_in),

.q_b (data_out),

.aclr0 (1'b0),

.aclr1 (1'b0),

.clocken1 (1'b1),

.clocken0 (1'b1),

.q_a (),

.data_b ({8{1'b1}}),

.rden_b (1'b1),

.wren_b (1'b0),

.byteena_b (1'b1),

.addressstall_a (1'b0),

.byteena_a (1'b1),

.addressstall_b (1'b0),

.clock1 (1'b1));

defparam

altsyncram_component.address_aclr_a = "NONE",

altsyncram_component.address_aclr_b = "NONE",

altsyncram_component.address_reg_b = "CLOCK0",

altsyncram_component.indata_aclr_a = "NONE",

altsyncram_component.intended_device_family = "Stratix",

altsyncram_component.lpm_type = "altsyncram",

//This is where a 32, 8-bit word is modified.

altsyncram_component.numwords_a = 32,

altsyncram_component.numwords_b = 32,

altsyncram_component.operation_mode = "DUAL_PORT",

altsyncram_component.outdata_aclr_b = "NONE",

altsyncram_component.outdata_reg_b = "CLOCK0",

altsyncram_component.power_up_uninitialized = "FALSE",

altsyncram_component.read_during_write_mode_mixed_ports =

"DONT_CARE",

altsyncram_component.widthad_a = 5,

altsyncram_component.widthad_b = 5,

//This is the width of the input port.

altsyncram_component.width_a = 8,

altsyncram_component.width_b = 8,

altsyncram_component.width_byteena_a = 1,

altsyncram_component.wrcontrol_aclr_a = "NONE";

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 55 56

Commenti su questo manuale

Nessun commento

Altera Designing With Low-Level Primitives Manuale Utente Pagina 17

Commenti su questo manuale

Prodotti e manuali riguardandi Strumenti di misura Altera Designing With Low-Level Primitives