Altera Designing With Low-Level Primitives Manuale Utente Scaricare il pdf (Pagina 9)

Altera Corporation 1–3

April 2007 Designing with Low-Level Primitives User Guide

Low-Level Primitive Design

In Example 1–2, the LCELL primitive separates the logic in your design.

The first code example and the resulting view from the Quartus II

Technology Map Viewer (Figure 1–1) show that the logic is merged

during the synthesis process.

Example 1–2. LCELL Primitive Separates Logic

module logic_merge(

clk,

addr,

data,

dataout

);

input clk;

input [3:0] addr;

input [2:0] data;

output[2:0] dataout;

reg [2:0] dataout;

wire temp_0;

wire temp_1;

wire temp_2;

wire temp_3;

wire temp_4;

wire temp_5;

wire temp_6;

assign temp_3 = addr[0] & addr[1] & addr[2] & addr[3];

assign temp_4 = addr[3] & addr[2] & addr[1] & addr[0];

assign temp_1 = addr[1] & addr[2] & addr[3];

assign temp_2 = temp_1 & addr[0];

assign temp_5 = temp_2 & data[0];

assign temp_6 = temp_3 & data[1];

assign temp_0 = temp_4 & data[2];

always@(posedge clk)

begin

dataout[2] <= temp_0;

end

always@(posedge clk)

begin

dataout[0] <= temp_5;

end

always@(posedge clk)

begin

dataout[1] <= temp_6;

end

endmodule

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