Altera Designing With Low-Level Primitives Manuale Utente Scaricare il pdf (Pagina 36)

2–14 Altera Corporation

Designing with Low-Level Primitives User Guide April 2007

Primitives

the default. Assigning –1 to slew_rate is equivalent to not setting the

parameter. Note that the primitive requires that all three ports (i, o, and

obar) are connected. Also note that all parameters are optional.

Example 2–10 shows a VHDL component instantiation example of an

ALT_OUTBUF_DIFF primitive.

Example 2–10. ALT_OUTBUF_DIFF Primitive, VHDL Component Instantiation

library ieee;

use ieee.std_logic_1164.all;

library altera;

use altera.altera_primitives_components.all;

entity test_outbuf is

port (

in1, in2 : in std_logic;

out1, out1_n : out std_logic

);

end test_outbuf;

architecture test of test_outbuf is

signal tmp: std_logic;

begin

inst : ALT_OUTBUF_DIFF

generic map (

IO_STANDARD => "LVDS",

LOCATION=> "IOBANK_3"

)

port map (

i => tmp,

o => out1,

obar => out1_ n

) ;

tmp <= in1 and in2;

end test;

ALT_OUTBUF_TRI_DIFF

This primitive allows you to name and connect positive and negative pins

when a differential I/O standard is used for a tri-statable output pin. You

can assign I/O standard, location, drive strength (current strength), slew

rate, and termination assignments, control bus hold circuitry, and enable

weak pull-up resistor on the output pins. An attempt to set any other

parameter will result in an error.

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Altera Designing With Low-Level Primitives Manuale Utente Pagina 36