Altera DDR SDRAM Controller Manuale Utente

101 Innovation DriveSan Jose, CA 95134www.altera.comDDR and DDR2 SDRAM Controller Compiler UserGuideSoftware Version: 9.0Document Date: March 2009

1–6 Chapter 1: About This CompilerInstallation and LicensingDDR and DDR2 SDRAM Controller Compiler User Guide March 2009 Altera CorporationFigure 1–2

C–2DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation1 Some of these constraints may conflict with constraints added by

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideD. Maximizing PerformanceTo achieve maximum performance, your design

D–2Adjust the PLL PhasesDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationAdjust the PLL PhasesThere is no automatic se

D–3Update the PLL Phases© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideUpdate the PLL PhasesAfter compilation you sh

D–4Update the PLL PhasesDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuidePreliminaryAdditional InformationRevision HistoryThe following table

Info–ii Additional InformationTypographic ConventionsDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationPreliminaryVisua

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide2. Getting StartedDesign FlowThe Altera DDR and DDR2 SDRAM Controller

2–2 Chapter 2: Getting StartedSOPC Builder Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationThe DDR and DDR

Chapter 2: Getting Started 2–3SOPC Builder Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideCreate a New Qu

2–4 Chapter 2: Getting StartedSOPC Builder Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation1 If you are ta

Chapter 2: Getting Started 2–5SOPC Builder Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide6. Turn on Adva

2–6 Chapter 2: Getting StartedSOPC Builder Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationSOPC Builder ge

Chapter 2: Getting Started 2–7SOPC Builder Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideEdit the PLLThe

2–8 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporationc

Chapter 2: Getting Started 2–9MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide2

Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device design

2–10 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Chapter 2: Getting Started 2–11MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

2–12 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Chapter 2: Getting Started 2–13MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

2–14 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Chapter 2: Getting Started 2–15MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

2–16 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Chapter 2: Getting Started 2–17MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

2–18 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Chapter 2: Getting Started 2–19MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideContentsChapter 1. About This CompilerRelease Information . . . .

2–20 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Chapter 2: Getting Started 2–21MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

2–22 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Chapter 2: Getting Started 2–23MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

2–24 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Chapter 2: Getting Started 2–25Set Up Licensing© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideSet Up LicensingYou ne

2–26 Chapter 2: Getting StartedSet Up LicensingDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide3. Functional DescriptionThe DDR and DDR2 SDRAM controllers instantia

3–2 Chapter 3: Functional DescriptionBlock DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationTable 3–1 shows

Chapter 3: Functional Description 3–3OpenCore Plus Time-Out Behavior© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideI

ivDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationMegaCore Verification . . . . . . . . . . . . . . . . . . . . . .

3–4 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationAll mega

Chapter 3: Functional Description 3–5Device-Level Description© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideIn the w

3–6 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFigure 3

Chapter 3: Functional Description 3–7Device-Level Description© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideDesignin

3–8 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationThe cont

Chapter 3: Functional Description 3–9Device-Level Description© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideFigure 3

3–10 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFigure

Chapter 3: Functional Description 3–11Device-Level Description© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideFigure

3–12 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFigure

Chapter 3: Functional Description 3–13Device-Level Description© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuidePLL Con

March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide1. About This CompilerRelease InformationTable 1–1 provides information

3–14 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFor Str

Chapter 3: Functional Description 3–15Device-Level Description© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideFigure

3–16 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationDLL Con

Chapter 3: Functional Description 3–17Device-Level Description© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideFigure

3–18 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationThe tes

Chapter 3: Functional Description 3–19Interfaces & Signals© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideFor Str

3–20 Chapter 3: Functional DescriptionInterfaces & SignalsDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationWritesF

Chapter 3: Functional Description 3–21Interfaces & Signals© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide1. The

3–22 Chapter 3: Functional DescriptionInterfaces & SignalsDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation1. The

Chapter 3: Functional Description 3–23Interfaces & Signals© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide4. The

1–2 Chapter 1: About This CompilerFeaturesDDR and DDR2 SDRAM Controller Compiler User Guide March 2009 Altera CorporationFeatures Support for industr

3–24 Chapter 3: Functional DescriptionInterfaces & SignalsDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation2. The

Chapter 3: Functional Description 3–25Interfaces & Signals© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideDDR SDR

3–26 Chapter 3: Functional DescriptionInterfaces & SignalsDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation2. An E

Chapter 3: Functional Description 3–27Interfaces & Signals© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide1. The

3–28 Chapter 3: Functional DescriptionInterfaces & SignalsDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationSignals

Chapter 3: Functional Description 3–29Interfaces & Signals© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideTable 3

3–30 Chapter 3: Functional DescriptionInterfaces & SignalsDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationTable 3

Chapter 3: Functional Description 3–31Parameters© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideParametersThe paramet

3–32 Chapter 3: Functional DescriptionParametersDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationMemoryTable 3–11 show

Chapter 3: Functional Description 3–33Parameters© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideController Table 3–13

Chapter 1: About This Compiler 1–3General DescriptionMarch 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideThe DDR SDRAM Cont

3–34 Chapter 3: Functional DescriptionParametersDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationTable 3–14 shows the

Chapter 3: Functional Description 3–35Parameters© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideTable 3–15 shows the

3–36 Chapter 3: Functional DescriptionParametersDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationTable 3–16 shows the

Chapter 3: Functional Description 3–37Parameters© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideTable 3–17 shows the

3–38 Chapter 3: Functional DescriptionParametersDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFor minimum timing re

Chapter 3: Functional Description 3–39Parameters© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideBoard TimingsTable 3–

3–40 Chapter 3: Functional DescriptionParametersDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationProject SettingsTable

Chapter 3: Functional Description 3–41MegaCore Verification© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideManual Tim

3–42 Chapter 3: Functional DescriptionMegaCore VerificationDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationTable 3–26

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideA. Manual Timing SettingsParametersTable A–1 shows the resynchronizat

1–4 Chapter 1: About This CompilerPerformance and Resource UtilizationDDR and DDR2 SDRAM Controller Compiler User Guide March 2009 Altera Corporation

A–2ParametersDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationTable A–2 shows the postamble options (DQS mode only).f

A–3Parameters© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideTable A–3 shows the capture options (non-DQS mode only).

A–4ResynchronizationDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationTable A–4 shows the timing analysis options. Resy

A–5Resynchronization© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideResynchronization RegistersFigure A–1 shows the r

A–6ResynchronizationDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFigure A–2 shows the resynchronization registers

A–7Resynchronization© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideFigure A–4 shows the resynchronization registers

A–8ResynchronizationDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFigure A–4 shows the resynchronization registers

A–9Resynchronization© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideTable A–5 shows the manual resynchronization para

A–10DQS PostambleDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationIntermediate Resynchronization RegistersFigure A–6 s

A–11DQS Postamble© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideThe DDR and DDR2 SDRAM Controller Compiler provides

Chapter 1: About This Compiler 1–5Installation and LicensingMarch 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideThe perform

A–12DQS PostambleDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFigure A–8 shows an example of how to choose the bes

A–13Examples© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideExamplesExample A–1 and Example A–2 show the generated PL

A–14ExamplesDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationExample A–3 and Example A–4 show the top-level design fil

A–15Examples© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideExample A–4 shows the top-level example design file with

A–16ExamplesDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideB. DDR SDRAM on the Nios DevelopmentBoard, Cyclone II EditionThis app

B–2DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation3. The DDR SDRAM device on the Nios Development Board, Cyclone II

B–3© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide6. The DDR SDRAM wizard automatically creates constraint scripts f

B–4DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideC. HardCopy II Design WalkthroughThis walkthrough explains the additi