Altera DDR SDRAM Controller Manuale Utente Scaricare il pdf (Pagina 87)

A–9

Resynchronization

Table A–5 shows the manual resynchronization parameters.

Figure A–5 on page A–9 shows an example of how to choose the best manual

resynchronization phase. In this example the best resynchronization phase is cycle =

0, phase = 270° , and the rising edge of write_clk.

This example is for CAS latency = 2. For CAS latency = 2.5, add 180° to the

resynchronization phase; for CAS latency = 3, add 1 cycle to the resynchronization

cycle.

Table A–5. Manual Resynchronization Parameters

Cycle Clock Edge Phase (° )

0, 1, 2, 3, 4, 5, 6 clk Rising 0 (1)

write_clk Falling 90

clk Falling 180

write_clk Rising (2) 270

Notes to Table A–5:

(1) Resynchronization cycle 0 phase 0 is defined as the first rising edge of clk capable of

resynchronizing the read data for CAS latency = 2.

(2) Use the intermediate resynchronization option to guarantee timing between the

resynchronization registers and registers on the system clock.

Figure A–5. Choosing the Best Resynchronization Phase

Note to Figure A–5:

(1) Figure 3–4, Figure 3–5, and Figure 3–6 on page 3–9 show these registers.

clk

012

270 0 180

write_clk

Theoretical Q Output

of DQ Capture Register

(see

Note 1

)

Actual Data Valid at

D Input of Resynchronization

Note 1

)

dqs (90 shifted)

Resynchronization

Phase

Resynchronization

Cycle

H/L

Theoretical Round Trip Delay

Safe Resynchronization Window

Best Resynchronization Phase

1 2 ... 82 83 84 85 86 87 88 89 90 91 92 ... 105 106

Commenti su questo manuale

Nessun commento

Altera DDR SDRAM Controller Manuale Utente Pagina 87

Commenti su questo manuale

Prodotti e manuali riguardandi Strumenti di misura Altera DDR SDRAM Controller