Altera DDR SDRAM Controller Manuale Utente Scaricare il pdf (Pagina 91)

A–13

Examples

Example A–1 and Example A–2 show the generated PLLs and the PLL outputs for the

following options:

■ Use fedback clock = On

■ Manual resynchronization control = On

■ Resynchronization clock setting = Dedicated

■ Manual postamble control = On

■ Postamble clock setting = Dedicated

Figure A–10. Inserting an Intermediate Postamble Register

QD QD QD

DQ DQ DQ DQ

Fedback

PLL

dq_capture inter_rdata

resynched_data

fedback_resynched_data

inter_rdata

dqs

postamble_clk

resynch_clk

clk

Fedback

Clock Input

System

PLL

Present when

Intermediate Postamble

Example A–1. System PLL and Clock Outputs

ddr_pll_stratixii g_stratixpll_ddr_pll_inst

(

.c0 (clk),

.c1 (write_clk),

.c2 (dedicated_resynch_or_capture_clk),

.inclk0 (clock_source)

);

Example A–2. Fedback PLL and Clock Outputs

ddr_pll_fb_stratixii g_stratixpll_ddr_fedback_pll_inst

(

.c0 (fedback_resynch_clk),

.c1 (dedicated_postamble_clk),

.inclk0 (fedback_clk_in)

);

1 2 ... 86 87 88 89 90 91 92 93 94 95 96 ... 105 106

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Altera DDR SDRAM Controller Manuale Utente Pagina 91

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