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Chapter 3: Functional Description 3–33
Parameters
© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
Controller
Table 3–13 shows the local interface options.
DQ bits per DQS pin 8 Bits The number of data (DQ) bits for each data strobe (DQS) pin. This
option depend on the type of memory selected. Memories either
support ×4 or ×8 mode. Stratix II and Stratix III devices support
both modes. Cyclone III devices do not support the DQS mode, as
the devices do not have the DQS-related circuitry.
Use ×4 floorplan files that
include DM pins
— — Two sets of recommended pins are provided for use with ×4
mode (four DQ per DQS) on the sides of Stratix II devices. If you
do not intend to use the memory DM pins, turn off this control to
give more available pins for your DDR SDRAM interface.
Registered DIMM /
Unbuffered memory
— — This option depends on the type of memory selected.
Select Registered DIMM for higher performance systems such as
servers, workstations, routers, and switches. To assure data
integrity, Registered DIMM uses additional devices: one to two
registers to latch address and command signals, and one PLL
clock buffer to adjust timing.
Registered DIMMs have their address and control lines buffered
on the DIMM to reduce signal loading. Because the registered
DIMM requires a buffer, they are more expensive than unbuffered
DIMMs. Unbuffered DIMMs do not buffer the address lines and
control lines, so they cost less and may be limited in the amount
the system may have installed because of system loading.
However an unbuffered DDR DIMM is able to operate one clock
cycle faster than a registered DIMM.
Note to Table 3–12:
(1) These are set by the device that you choose in the Presets list.
Table 3–12. Memory Property Parameters (Part 2 of 2) (Note 1)
Parameter Range Units Description
Table 3–13. Local Interface
Parameter Range Description
Local Interface Native or Avalon Specifies the local side interface between the user logic and the memory
controller, refer to “Interface Description” on page 3–19.
This interface refers to the connection of the user logic (driver) to the
controller. There are few differences between the two interfaces in
performing read and write transactions. The Avalon-MM interface is
supported by SOPC builder (refer to the Avalon Interface Specifications).
For non-SOPC builder designs, you can build the driver logic to interface
to the controller with either the native interface (refer to “Interface
Description” on page 3–19) or the Avalon-MM interface.
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Software Version: 9.0 1
- Document Date: March 2009 1
- UG-DDRSDRAM-10.0 2
- Contents 3
- 1. About This Compiler 5
- Features 6
- General Description 6
- Note to Figure 1–1: 7
- Note to Table 1–3: 8
- Installation and Licensing 9
- OpenCore Plus Evaluation 10
- 2. Getting Started 11
- SOPC Builder Design Flow 12
- Parameterize 14
- Constraints 15
- Add/Update Component 15
- Create Your Top-Level Design 16
- Edit the PLL 17
- Program a Device 18
- Figure 2–1. System Naming 24
- Set Up Simulation 25
- Generate 25
- Simulate the Example Design 27
- Notes to Table 2–2: 29
- Notes to Table 2–3: 30
- Notes to Table 2–4: 31
- Compile the Example Design 32
- Implement Your Design 34
- Set Up Licensing 35
- Control Logic 37
- Datapath 38
- Device-Level Description 41
- Figure 3–3. Datapath Timing 42
- Designing Your Own Controller 43
- DQS Group Block Diagrams 44
- Notes to Figure 3–4: 45
- Notes to Figure 3–5: 46
- Notes to Figure 3–6: 47
- Notes to Figure 3–7: 48
- PLL Configurations 49
- Stratix II Device 50
- Stratix Device 51
- Cyclone II Device 51
- Cyclone Device 51
- DLL Configurations 52
- Example Design 52
- Notes to Table 3–5: 53
- Interface Description 55
- Figure 3–13. Writes 56
- Interfaces & Signals 57
- DDR SDRAM 58
- Interface 58
- Local Interface 58
- [1] [3][2] [5][4] 58
- [1] [2] [3] [4] [6][5] 59
- User Refresh Control 60
- 200 clock cycles 63
- Note to Table 3–7: 65
- Parameters 67
- Controller 69
- Note to Table 3–15: 71
- Controller Timings 73
- Memory Timings 74
- Board Timings 75
- Project Settings 76
- Manual Timings 77
- Simulation Testing 77
- Hardware Testing 77
- (MT46V8M16-75Z) 78
- A. Manual Timing Settings 79
- Resynchronization 82
- Resynchronization Registers 83
- Notes to Figure A–2: 84
- Notes to Figure A–3: 85
- Notes to Figure A–4: 86
- Notes to Table A–5: 87
- Note to Figure A–5: 87
- DQS Postamble 88
- Postamble Logic 89
- System Clock 90
- Postamble 90
- Examples 91
- Board, Cyclone II Edition 95
- D. Maximizing Performance 101
- Adjust the PLL Phases 102
- Assign Pins 102
- Place the Fedback PLL 102
- Update the PLL Phases 103
- Additional Information 105
- Typographic Conventions 106
- Preliminary 106
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