Altera CPRI v6.0 MegaCore Function Manuale Utente Pagina 21
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Parameter Range Default
Setting
Parameter Description
Enable direct ctrl_axc
access interface
• On
• Off
Off
Turn on this parameter to include a dedicated
interface to access the Ctrl_AxC subchannels in
the CPRI frame.
Enable direct vendor
specific access
interface
• On
• Off
Off
Turn on this parameter to include a dedicated
interface to access the VS subchannels in the
CPRI frame.
Enable start-up
sequence state
machine
• On
• Off
Off
Turn on this parameter to include a start-up
sequence state machine in the CPRI v6.0 IP core.
Enable L1 inband
protocol negotiator
• On
• Off
Off
Turn on this parameter to include a negotiator
block that performs auto-negotiation of L1
inband protocol version (communicated in CPRI
frame position Z.2.0) and L2 C&M rates
(communicated in CPRI frame positions Z.66.0
and Z.194.0).
This parameter is available when you turn on
Enable start-up sequence state machine.
Enable real-time
vendor specific
interface (R-16A)
• On
• Off
Off
Turn on this parameter to include a dedicated
interface to access the RTVS subchannel in the
CPRI frame.
This parameter is available when you specify a
CPRI line bit rate of 10137.6 Mbps.
Enable Z.130.0 access
interface
• On
• Off
Off
Turn on this parameter to include a dedicated L1
control and status interface to communicate the
contents of the CPRI frame Z.130.0 word, which
includes alarms and reset signals.
L2 Features
Enable direct HDLC
serial interface
• On
• Off
Off
Turn on this parameter to include a dedicated
interface to communicate the contents of the slow
C&M subchannels.
For full HDLC communication, you must
connect a user-defined HDLC module to this
interface.
Enable IEEE 802.3
100BASE-X 100Mbps
MII
• On
• Off
Off
Turn on this parameter to include an MII port to
communicate with the fast C&M (Ethernet) CPRI
subchannel.
For full Ethernet communication, you must
connect a user-defined Ethernet MAC to this
interface.
2-10
CPRI v6.0 IP Core Parameters
UG-01156
2014.08.18
Altera Corporation
Getting Started with the CPRI v6.0 IP Core
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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