Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manuale Utente Scaricare il pdf (Pagina 52)

Altera Corporation A–2

July 2010 Nios II Embedded Evaluation Kit, Cyclone III Edition

The Pixel Format Converter subsystem assumes that the frame-buffer is

storing 32-bit pixel values in (0:R:G:B) (8:8:8:8) format. The

sync-generator, however, accepts 24-bit values. So the Pixel Format

Converter takes-in a stream of 32-bit (0:R:G:B) pixels and produces a

stream of 24-bit (R:G:B) values. This is done by throwing-away the

unused 8 bits.

Once the Pixel Format Converter has produced a stream of 24-bit (8:8:8)

(R:G:B) values, the data format adapter serializes the data into a stream of

8-bit (R, then G, then B) values. This is the input to the sync generator

block which produces the horizontal and vertical timing signals.

1 The video pipeline used in the Nios II Standard System is just

one implementation for video systems. FPGAs give you the

power of flexibility to change this with just a few lines of code.

For example, the next section describes what is necessary to

support a 5:6:5 pixel format.

Get the full LCD

controller

Application Note

For more information about the video pipeline and LCD controller, refer

to AN527: Implementing an LCD Controller.

Creating a new

5:6:5 Pixel-

Format

component

The Nios II Standard System is designed to use a 32-bit 0:R:G:B data

format. Suppose you wanted to change the entire display subsystem to

work with 16-bit 5:6:5 pixels instead of 32-bit 0:R:G:B pixels. This can be

accomplished with a few simple steps:

1. Copy the Nios II Standard System into your own project directory.

2. Create a new Verilog module called pixel_converter_565 starting

from the Verilog in altera_avalon_pixel_converter.v, modify this

Verilog so it has a 16-bit data_in port and a 24-bit data_out port. All

the other ports remain the same. You create the data_out value by

inserting 8 new bits (3xR, 2xG, and 3xB) at the right points in the

16-bit word to “pad” it to a 24-bit word. You can use either zero- or

LSB-padding.

3. Import your Verilog module into SOPC Builder using the

Component Editor.

4. From an Nios II Standard System, replace the existing Pixel Format

Converter with your new pixel_converter_565 component.

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Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manuale Utente Pagina 52