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Chapter : Info–5

Revision History

August 2014 Altera Corporation IP Compiler for PCI Express User Guide

November

2009

9.1

■ Added support for Cyclone IV GX and HardCopy IV GX.

■ Added ability to parameterize the ALTGX Megafunction from the PCI Express IP core.

■ Added ability to run the hard IP implementation Gen1 ×1 application clock at 62.5 MHz,

presumably to save power.

■ Added the following signals to the IP core:

xphy_pll_areset

xphy_pll_locked

nph_alloc_1cred_vc0,

npd_alloc_1cred_vc1,

npd_cred_vio_vc0

, and

nph_cred_vio_vc1

■ Clarified use of qword alignment for TLPs in Chapter 5, IP Core Interfaces.

■ Updated Table 5–15 on page 5–32 to include cross-references to the appropriate PCI

Express configuration register table and provide more information about the various fields.

■ Corrected definition of the definitions of

cfg_devcsr[31:0]

in Table 5–15 on page 5–32.

cfg_devcsr[31:16]

is device status.

cfg_devcsr[15:0]

is device control.

■ Corrected definition of Completer abort in Table 12–4 on page 12–3. The error is reported on

cpl_error[2]

■ Added 2 unexpected completions to Table 12–4 on page 12–3.

■ Updated Figure 7–9 on page 7–11 to show

clk

and

AvlClk_L

■ Added detailed description of the

tx_cred

<n> signal.

■ Corrected Table 3–2 on page 3–6. Expansion ROM is non-prefetchable.

March 2009

9.0

■ Expanded discussion of “Serial Interface Signals” on page 5–53.

■ Clarified Table 1–9 on page 1–13. All cores support ECC with the exception of Gen2 ×8. The

internal clock of the ×8 core runs at 500 MHz.

■ Added warning about use of

test_out

and

test_in

buses.

■ Moved debug signals

rx_st_fifo_full0

and

rx_st_fifo_empty0

to the test bus.

Documentation for these signals moved from the Signals chapter to Appendix B, Test Port

Interface Signals.

Date Version Changes Made SPR

1 2 ... 360 361 362 363 364 365 366 367 368 369 370 371 372

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