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Chapter 5: IP Core Interfaces 5–15

Avalon-ST Interface

August 2014 Altera Corporation IP Compiler for PCI Express User Guide

64- or 128-Bit Avalon-ST TX Port

Table 5–4 describes the signals that comprise the Avalon-ST TX Datapath.

Table 5–4. 64- or 128-Bit Avalon-ST TX Datapath (Part 1 of 3)

Signal Width Dir

Avalon-ST

Type

Description

tx_st_ready<n>

(1) (2) 1O

ready

Indicates that the PCIe core is ready to accept data for

transmission. The core deasserts this signal to throttle

the data stream. In the hard IP implementation,

tx_st_ready<n>

may be asserted during reset. The

application should wait at least 2 clock cycles after the

reset is released before issuing packets on the Avalon-ST

TX interface. The

reset_status

signal can also be used

to monitor when the IP core has come out of reset.

When

tx_st_ready

<n>,

tx_st_valid

<n> and

tx_st_data

<n> are registered (the typical case) Altera

recommends a

readyLatency

of 2 cycles to facilitate

timing closure; however, a

readyLatency

of 1 cycle is

possible.

To facilitate timing closure, Altera recommends that you

tx_st_ready

and

tx_st_valid

signals. If no other delays are added to the ready-valid

latency, this corresponds to a

readyLatency

of 2.

tx_st_valid<n>

(2) 1I

valid

Clocks

tx_st_data<n>

into the core. Between

tx_st_sop<n>

and

tx_st_eop<n>

, must be asserted if

tx_st_ready<n>

is asserted. When

tx_st_ready<n>

deasserts, this signal must deassert within 1, 2, or 3

clock cycles for soft IP implementation and within 1 or 2

clock cycles for hard IP

tx_st_valid<n>

(2) 1I

valid

implementation. When

tx_st_ready<n>

reasserts, and

tx_st_data<n>

is in mid-TLP, this signal must reassert

within 3 cycles for soft IP and 2 cycles for the hard IP

implementation. Refer to Figure 5–24 on page 5–21 for

the timing of this signal.

To facilitate timing closure, Altera recommends that you

tx_st_ready

and

tx_st_valid

signals. If no other delays are added to the ready-valid

latency, this corresponds to a

readyLatency

of 2

tx_st_data<n>

64,

128

data

Data for transmission.Transmit data bus. Refer to

Figure 5–18 through Figure 5–23 for the mapping of TLP

packets to

tx_st_data<n>

. Refer to Figure 5–24 for the

timing of this interface. When using a 64-bit Avalon-ST

bus, the width of

tx_st_data

is 64. When using 128-bit

Avalon-ST bus, the width of

tx_st_data

is 128. The

application layer must provide a properly formatted TLP

on the TX interface. The mapping of message TLPs is the

same as the mapping of transaction layer TLPs with 4

dword headers. The number of data cycles must be

correct for the length and address fields in the header.

Issuing a packet with an incorrect number of data cycles

results in the TX interface hanging and unable to accept

further requests.

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