Altera Stratix IV GX FPGA Development Board Manuale Utente Scaricare il pdf (Pagina 79)

August 2012 Altera Corporation Stratix IV GX FPGA Development Board

Reference Manual

Additional Information

This chapter provides additional information about the document and Altera.

Document Revision History

The following table shows the revision history for this document.

Date Version Changes

August 2012 2.3

■ Corrected the schematic signal names for board references J2.108 and J2.109 in

Table 2–38.

■ Added

DDR3BOT_RSTn

signal in Table 2–46.

■ Added

DDR3TOP_RSTn

signal in Table 2–48.

■ Maintenance release.

August 2010 2.2

■ Updated the manufacturing part number of the flash device in Table 2–57.

■ Converted document to new frame template and made textual and style changes.

June 2010 2.1

■ Updated Stratix IV GX FPGA development board block diagram in Figure 1–1.

■ Updated the description of the HDMI video port (J11) in Table 2–1, and in “HDMI Video

Output” on page 2–42.

■ Updated the manufacturing part number of the Stratix IV GX device in Table 2–3.

■ Added “Single-Die Flash Version Differences” on page A–1 to document the replacement

of dual-die 512-Mb flash with a single-die flash device.

November 2009 2.0

■ Updated MAX II CPLD EPM2210 System Controller block diagram in Figure 2–3.

■ Added two I/O signals,

CLK100_SDA

and

CLK100_SCL

in Table 2–6.

■ Replaced 100-MHz fixed frequency oscillator (X6) with a programmable oscillator

described in clocking section.

■ Increased SRAM frequency to 250 MHz.

■ Corrected schematic signal names in Table 2–46 and Table 2–48.

■ Added manufacturing information for QDRII+ top port 1 SRAM memory in Table 2–51

and Table 2–53.

■ Updated voltage values for the power rails measurement in Table 2–58.

■ Updated power distribution system in Figure 2–15.

■ Added an appendix to document the board revision change (engineering silicon to

production silicon revisions).

August 2009 1.3

■ Corrected DDR3 top port schematic signal names in Table 2–48.

July 2009 1.2

■ Added HSMA present LED and HSMB present LED board components, and corrected

SSRAM x36 Memory description in Table 2–1.

■ Updated I/O count in Table 2–4.

■ Corrected PCI Express edge description in Table 2–20.

■ Corrected LVDS schematic signal names in Table 2–37 and Table 2–38.

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