Altera Stratix IV GX FPGA Development Board Manuale Utente Scaricare il pdf (Pagina 48)

2–40 Chapter 2: Board Components

Components and Interfaces

Stratix IV GX FPGA Development Board August 2012 Altera Corporation

Reference Manual

J2.37 JTAG data output

HSMB_JTAG_TDO

2.5-V —

J2.38 JTAG data input

HSMB_JTAG_TDI

2.5-V —

J2.39 Dedicated CMOS clock out

HSMB_CLK_OUT0

2.5-V AK29

J2.40 Dedicated CMOS clock in

HSMB_CLK_IN0

2.5-V AA35

J2.41 Dedicated CMOS I/O bit 0

HSMB_D0

2.5-V AP10

J2.42 Dedicated CMOS I/O bit 1

HSMB_D1

2.5-V AN10

J2.43 Dedicated CMOS I/O bit 2

HSMB_D2

2.5-V AW8

J2.44 Dedicated CMOS I/O bit 3

HSMB_D3

2.5-V AV8

J2.47 LVDS TX bit 0 or CMOS bit 4

HSMB_TX_D_P0

LVDS or 2.5-V W12

J2.48 LVDS RX bit 0 or CMOS bit 5

HSMB_RX_D_P0

LVDS or 2.5-V W8

J2.49 LVDS TX bit 0n or CMOS bit 6

HSMB_TX_D_N0

LVDS or 2.5-V W11

J2.50 LVDS RX bit 0n or CMOS bit 7

HSMB_RX_D_N0

LVDS or 2.5-V W7

J2.53 LVDS TX bit 1 or CMOS bit 8

HSMB_TX_D_P1

LVDS or 2.5-V V12

J2.54 LVDS RX bit 1 or CMOS bit 9

HSMB_RX_D_P1

LVDS or 2.5-V V6

J2.55 LVDS TX bit 1n or CMOS bit 10

HSMB_TX_D_N1

LVDS or 2.5-V V11

J2.56 LVDS RX bit 1n or CMOS bit 11

HSMB_RX_D_N1

LVDS or 2.5-V U5

J2.59 LVDS TX bit 2 or CMOS bit 12

HSMB_TX_D_P2

LVDS or 2.5-V V10

J2.60 LVDS RX bit 2 or CMOS bit 13

HSMB_RX_D_P2

LVDS or 2.5-V R7

J2.61 LVDS TX bit 2n or CMOS bit 14

HSMB_TX_D_N2

LVDS or 2.5-V V9

J2.62 LVDS RX bit 2n or CMOS bit 15

HSMB_RX_D_N2

LVDS or 2.5-V P6

J2.65 LVDS TX bit 3 or CMOS bit 16

HSMB_TX_D_P3

LVDS or 2.5-V U10

J2.66 LVDS RX bit 3 or CMOS bit 17

HSMB_RX_D_P3

LVDS or 2.5-V R6

J2.67 LVDS TX bit 3n or CMOS bit 18

HSMB_TX_D_N3

LVDS or 2.5-V T9

J2.68 LVDS RX bit 3n or CMOS bit 19

HSMB_RX_D_N3

LVDS or 2.5-V R5

J2.71 LVDS TX bit 4 or CMOS bit 20

HSMB_TX_D_P4

LVDS or 2.5-V T10

J2.72 LVDS RX bit 4 or CMOS bit 21

HSMB_RX_D_P4

LVDS or 2.5-V N6

J2.73 LVDS TX bit 4n or CMOS bit 22

HSMB_TX_D_N4

LVDS or 2.5-V R10

J2.74 LVDS RX bit 4n or CMOS bit 23

HSMB_RX_D_N4

LVDS or 2.5-V N5

J2.77 LVDS TX bit 5 or CMOS bit 24

HSMB_TX_D_P5

LVDS or 2.5-V R9

J2.78 LVDS RX bit 5 or CMOS bit 25

HSMB_RX_D_P5

LVDS or 2.5-V N8

J2.79 LVDS TX bit 5n or CMOS bit 26

HSMB_TX_D_N5

LVDS or 2.5-V R8

J2.80 LVDS RX bit 5n or CMOS bit 27

HSMB_RX_D_N5

LVDS or 2.5-V N7

J2.83 LVDS TX bit 6 or CMOS bit 28

HSMB_TX_D_P6

LVDS or 2.5-V N9

J2.84 LVDS RX bit 6 or CMOS bit 29

HSMB_RX_D_P6

LVDS or 2.5-V M6

J2.85 LVDS TX bit 6n or CMOS bit 30

HSMB_TX_D_N6

LVDS or 2.5-V P8

J2.86 LVDS RX bit 6n or CMOS bit 31

HSMB_RX_D_N6

LVDS or 2.5-V L5

J2.89 LVDS TX bit 7 or CMOS bit 32

HSMB_TX_D_P7

LVDS or 2.5-V N11

J2.90 LVDS RX bit 7 or CMOS bit 33

HSMB_RX_D_P7

LVDS or 2.5-V K6

Table 2–38. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference

Description Schematic Signal

Name

I/O Standard

Stratix IV GX

Device

Pin Number

1 2 ... 43 44 45 46 47 48 49 50 51 52 53 ... 81 82

Commenti su questo manuale

Nessun commento

Altera Stratix IV GX FPGA Development Board Manuale Utente Pagina 48

Commenti su questo manuale

Prodotti e manuali riguardandi Strumenti di misura Altera Stratix IV GX FPGA Development Board