Altera Stratix IV GX FPGA Development Board Manuale Utente Scaricare il pdf (Pagina 40)

2–32 Chapter 2: Board Components

Components and Interfaces

Stratix IV GX FPGA Development Board August 2012 Altera Corporation

Reference Manual

Figure 2–9 shows the PCI Express reference clock levels.

The JTAG and SMB are optional signals in the PCI Express specification. Both types of

signals are wired to the Stratix IV GX device but are not required for normal

operation. Table 2–34 lists the PCI Express pin assignments. The signal names and

directions are relative to the Stratix IV GX FPGA.

Figure 2–9. PCI Express Reference Clock Levels

MAX

= 1.15 V

CROSS MAX

= 550 mV

CROSS MIN

= 250 mV

MIN

= –0.30 V

REFCLK –

REFCLK +

Table 2–34. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board Reference Description Schematic Signal

Name

I/O Standard

Stratix IV GX

Device

Pin Number

J17.A47 Add-in card transmit bus

PCIE_TX_P7

1.4-V PCML P36

J17.A48 Add-in card transmit bus

PCIE_TX_N7

1.4-V PCML P37

J17.A43 Add-in card transmit bus

PCIE_TX_P6

1.4-V PCML T36

J17.A44 Add-in card transmit bus

PCIE_TX_N6

1.4-V PCML T37

J17.A39 Add-in card transmit bus

PCIE_TX_P5

1.4-V PCML AB36

J17.A40 Add-in card transmit bus

PCIE_TX_N5

1.4-V PCML AB37

J17.A35 Add-in card transmit bus

PCIE_TX_P4

1.4-V PCML AD36

J17.A36 Add-in card transmit bus

PCIE_TX_N4

1.4-V PCML AD37

J17.A29 Add-in card transmit bus

PCIE_TX_P3

1.4-V PCML AF36

J17.A30 Add-in card transmit bus

PCIE_TX_N3

1.4-V PCML AF37

J17.A25 Add-in card transmit bus

PCIE_TX_P2

1.4-V PCML AH36

J17.A26 Add-in card transmit bus

PCIE_TX_N2

1.4-V PCML AH37

J17.A21 Add-in card transmit bus

PCIE_TX_P1

1.4-V PCML AP36

J17.A22 Add-in card transmit bus

PCIE_TX_N1

1.4-V PCML AP37

J17.A16 Add-in card transmit bus

PCIE_TX_P0

1.4-V PCML AT36

J17.A17 Add-in card transmit bus

PCIE_TX_N0

1.4-V PCML AT37

J17.B45 Add-in card receive bus

PCIE_RX_P7

1.4-V PCML R38

J17.B46 Add-in card receive bus

PCIE_RX_N7

1.4-V PCML R39

J17.B41 Add-in card receive bus

PCIE_RX_P6

1.4-V PCML U38

J17.B42 Add-in card receive bus

PCIE_RX_N6

1.4-V PCML U39

J17.B37 Add-in card receive bus

PCIE_RX_P5

1.4-V PCML AC38

J17.B38 Add-in card receive bus

PCIE_RX_N5

1.4-V PCML AC39

J17.B33 Add-in card receive bus

PCIE_RX_P4

1.4-V PCML AE38

J17.B34 Add-in card receive bus

PCIE_RX_N4

1.4-V PCML AE39

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 81 82

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Altera Stratix IV GX FPGA Development Board Manuale Utente Pagina 40

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