Altera Stratix IV GX FPGA Development Board Manuale Utente Scaricare il pdf (Pagina 49)

Chapter 2: Board Components 2–41

Components and Interfaces

August 2012 Altera Corporation Stratix IV GX FPGA Development Board

Reference Manual

J2.91 LVDS TX bit 7n or CMOS bit 34

HSMB_TX_D_N7

LVDS or 2.5-V N10

J2.92 LVDS RX bit 7n or CMOS bit 35

HSMB_RX_D_N7

LVDS or 2.5-V K5

J2.95 LVDS or CMOS clock out 1 or CMOS bit 36

HSMB_CLK_OUT_P1

LVDS or 2.5-V K8

J2.96 LVDS or CMOS clock in 1 or CMOS bit 37

HSMB_CLK_IN_P1

LVDS or 2.5-V AB6

J2.97 LVDS or CMOS clock out 1 or CMOS bit 38

HSMB_CLK_OUT_N1

LVDS or 2.5-V J8

J2.98 LVDS or CMOS clock in 1 or CMOS bit 39

HSMB_CLK_IN_N1

LVDS or 2.5-V AA5

J2.101 LVDS TX bit 8 or CMOS bit 40

HSMB_TX_D_P8

LVDS or 2.5-V M8

J2.102 LVDS RX bit 8 or CMOS bit 41

HSMB_RX_D_P8

LVDS or 2.5-V J6

J2.103 LVDS TX bit 8n or CMOS bit 42

HSMB_TX_D_N8

LVDS or 2.5-V M7

J2.104 LVDS RX bit 8n or CMOS bit 43

HSMB_RX_D_N8

LVDS or 2.5-V J5

J2.107 LVDS TX bit 9 or CMOS bit 44

HSMB_TX_D_P9

LVDS or 2.5-V L8

J2.108 LVDS RX bit 9 or CMOS bit 45

HSMB_RX_D_P9

LVDS or 2.5-V G8

J2.109 LVDS TX bit 9n or CMOS bit 46

HSMB_TX_D_N9

LVDS or 2.5-V L7

J2.110 LVDS RX bit 9n or CMOS bit 47

HSMB_RX_D_N9

LVDS or 2.5-V F8

J2.113 LVDS TX bit 10 or CMOS bit 48

HSMB_TX_D_P10

LVDS or 2.5-V K7

J2.114 LVDS RX bit 10 or CMOS bit 49

HSMB_RX_D_P10

LVDS or 2.5-V G6

J2.115 LVDS TX bit 10n or CMOS bit 50

HSMB_TX_D_N10

LVDS or 2.5-V J7

J2.116 LVDS RX bit 10n or CMOS bit 51

HSMB_RX_D_N10

LVDS or 2.5-V F6

J2.119 LVDS TX bit 11 or CMOS bit 52

HSMB_TX_D_P11

LVDS or 2.5-V K9

J2.120 LVDS RX bit 11 or CMOS bit 53

HSMB_RX_D_P11

LVDS or 2.5-V G5

J2.121 LVDS TX bit 11n or CMOS bit 54

HSMB_TX_D_N11

LVDS or 2.5-V J9

J2.122 LVDS RX bit 11n or CMOS bit 55

HSMB_RX_D_N11

LVDS or 2.5-V F5

J2.125 LVDS TX bit 12 or CMOS bit 56

HSMB_TX_D_P12

LVDS or 2.5-V H7

J2.126 LVDS RX bit 12 or CMOS bit 57

HSMB_RX_D_P12

LVDS or 2.5-V F7

J2.127 LVDS TX bit 12n or CMOS bit 58

HSMB_TX_D_N12

LVDS or 2.5-V G7

J2.128 LVDS RX bit 12n or CMOS bit 59

HSMB_RX_D_N12

LVDS or 2.5-V E7

J2.131 LVDS TX bit 13 or CMOS bit 60

HSMB_TX_D_P13

LVDS or 2.5-V M10

J2.132 LVDS RX bit 13 or CMOS bit 61

HSMB_RX_D_P13

LVDS or 2.5-V G9

J2.133 LVDS TX bit 13n or CMOS bit 62

HSMB_TX_D_N13

LVDS or 2.5-V L10

J2.134 LVDS RX bit 13n or CMOS bit 63

HSMB_RX_D_N13

LVDS or 2.5-V F9

J2.137 LVDS TX bit 14 or CMOS bit 64

HSMB_TX_D_P14

LVDS or 2.5-V R12

J2.138 LVDS RX bit 14 or CMOS bit 65

HSMB_RX_D_P14

LVDS or 2.5-V D7

J2.139 LVDS TX bit 14n or CMOS bit 66

HSMB_TX_D_N14

LVDS or 2.5-V R11

J2.140 LVDS RX bit 14n or CMOS bit 67

HSMB_RX_D_N14

LVDS or 2.5-V C7

J2.143 LVDS TX bit 15 or CMOS bit 68

HSMB_TX_D_P15

LVDS or 2.5-V T13

J2.144 LVDS RX bit 15 or CMOS bit 69

HSMB_RX_D_P15

LVDS or 2.5-V D8

J2.145 LVDS TX bit 15n or CMOS bit 70

HSMB_TX_D_N15

LVDS or 2.5-V T12

J2.146 LVDS RX bit 15n or CMOS bit 71

HSMB_RX_D_N15

LVDS or 2.5-V C8

Table 2–38. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board

Reference

Description Schematic Signal

Name

I/O Standard

Stratix IV GX

Device

Pin Number

1 2 ... 44 45 46 47 48 49 50 51 52 53 54 ... 81 82

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Altera Stratix IV GX FPGA Development Board Manuale Utente Pagina 49

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