Altera Stratix IV GX FPGA Development Board Manuale Utente Scaricare il pdf (Pagina 67)

Chapter 2: Board Components 2–59

Memory

August 2012 Altera Corporation Stratix IV GX FPGA Development Board

Reference Manual

U30.N6 Address bus

FSM_A8

2.5-V AT34

U30.B10 Address bus

FSM_A7

2.5-V AE27

U30.B2 Address bus

FSM_A6

2.5-V AD27

U30.A10 Address bus

FSM_A5

2.5-V AP34

U30.A2 Address bus

FSM_A4

2.5-V AN33

U30.P6 Address bus

FSM_A3

2.5-V AD26

U30.R6 Address bus

FSM_A2

2.5-V AC26

U30.M2 Data bus

FSM_D31

2.5-V T28

U30.M1 Data bus

FSM_D30

2.5-V R28

U30.L2 Data bus

FSM_D29

2.5-V F32

U30.L1 Data bus

FSM_D28

2.5-V E32

U30.K2 Data bus

FSM_D27

2.5-V L31

U30.K1 Data bus

FSM_D26

2.5-V K31

U30.J2 Data bus

FSM_D25

2.5-V F31

U30.J1 Data bus

FSM_D24

2.5-V E31

U30.G2 Data bus

FSM_D23

2.5-V N29

U30.G1 Data bus

FSM_D22

2.5-V M29

U30.F2 Data bus

FSM_D21

2.5-V H31

U30.F1 Data bus

FSM_D20

2.5-V G31

U30.E2 Data bus

FSM_D19

2.5-V N30

U30.E1 Data bus

FSM_D18

2.5-V M30

U30.D2 Data bus

FSM_D17

2.5-V D33

U30.D1 Data bus

FSM_D16

2.5-V C33

U30.G11 Data bus

FSM_D15

2.5-V N31

U30.G10 Data bus

FSM_D14

2.5-V M31

U30.F11 Data bus

FSM_D13

2.5-V C32

U30.F10 Data bus

FSM_D12

2.5-V B32

U30.E11 Data bus

FSM_D11

2.5-V J32

U30.E10 Data bus

FSM_D10

2.5-V H32

U30.D11 Data bus

FSM_D9

2.5-V D35

U30.D10 Data bus

FSM_D8

2.5-V C35

U30.M11 Data bus

FSM_D7

2.5-V N28

U30.M10 Data bus

FSM_D6

2.5-V M28

U30.L11 Data bus

FSM_D5

2.5-V D31

U30.L10 Data bus

FSM_D4

2.5-V C31

U30.K11 Data bus

FSM_D3

2.5-V K30

U30.K10 Data bus

FSM_D2

2.5-V J30

U30.J11 Data bus

FSM_D1

2.5-V D34

U30.J10 Data bus

FSM_D0

2.5-V C34

Table 2–54. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)

Board Reference Description

Schematic Signal Name

I/O Standard

Stratix IV GX Device

Pin Number

1 2 ... 62 63 64 65 66 67 68 69 70 71 72 ... 81 82

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Altera Stratix IV GX FPGA Development Board Manuale Utente Pagina 67

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